A typical digital low-dropout regulator (DLDO) that is clocked with a fixed frequency suffers from the trade-offs between power, speed, and stability. This paper proposes a DLDO that achieves both fast settling and low power consumption without limit-cycle oscillation (LCO) by adaptively changing the clock frequency and eventually turning off the clock in the steady state. The proposed LDO also features an inverter-based droop-compensation circuit for output-capacitor-free operation. The proposed LDO designed in a 28-nm CMOS process achieves a 70-ns settling time and a 137-mV droop voltage for the 400-mA load current transition with a 2.6-ns edge time, which translates to the figure of merit of 4.8 fs.

An output-capacitor-free NMOS digital LDO (DLDO) using gate driving strength modulation (GDSM) is described. The proposed DLDO is mainly based on the time-driven topology while the GDSM changes the gate driving level adaptively according to the load current condition. The proposed GDSM lowers the gate driving level in the light load condition which improves the load transient response, widens the load current dynamic range, and reduces the output voltage ripple. A droop detector combined with the modulation scheme is also proposed to further improve the undershoot and recovery time. The proposed DLDO has been implemented in 28 nm CMOS and the 20,000$\times$load range is obtained even with 256 unity power switch arrays. When the load current changes from 5 mA to 85 mA, the$V_{OUT}$droop and recovery time are 130 mV and 2.5$\mu $s, which are 4.92$\times$and 70$\times$improvements compared to the baseline time-driven DLDO, respectively.

Zero-Crossing-Based Integrators (ZCBIs) are energy- efficient alternatives to conventional switched-capacitor integrators that are typically implemented using operational transconductance amplifiers (OTAs). However, ZCBIs suffer from signaldependent overshoot errors and increased dynamic power consumption due to inherent reset operation. This paper presents a ZCBI that employs a bidirectional two-phase charging scheme and performs the reset operation selectively. A 3rd-order DeltaSigma modulator has been fabricated in a 28-nm CMOS technology using the proposed integrators. The prototype modulator achieves 67-dB SNR and 63-dB SNDR over the bandwidth of 196 kHz with an oversampling ratio of 64. It consumes 184 pW, which translates to the figure-of-merits of 154 dB (FoMs) and 390 fJ/conv-step (FoMw).