This paper introduces a Dynamic Overload Surge Adjustment Protection (DOSAP) system aimed at improving the safety and reliability of electrical appliances in both industrial and residential settings. The DOSAP system features a microcontroller that monitors and calculates overload limits in real time, with easy integration into SCADA systems via UART. It provides extensive protection against both low and high voltage, as well as over-current issues, using the XGBoost machine learning model to dynamically predict and adjust overload thresholds. This novel approach enhances protection accuracy and operational efficiency by minimizing the need for manual intervention and adapting to changing electrical conditions.

General-purpose graphical processing units (GPGPUs) have become increasingly valuable platforms for accelerating parallel deep learning applications in recent years. GPUs are energy efficient if the software utilizes all usable resources; however, there are no hardware frameworks to adjust resources according to the application’s requirements. In this paper, we address a robust methodology for optimizing the structure of GPGPUs using machine learning (ML) techniques. The candidate model allows the use of output measurements from the base GPU configuration to determine the optimal GPU resources between three classes (large, medium, and small). We infer from the experimental results that, while we can achieve substantial power-aware computing, they can be significant while running the program on its suitable GPU setup. The ML-classification approach is tested under different CUDA application workloads to validate its effectiveness as well as GPU energy consumption and instruction per cycle metrics.

The 3D design of SRAM LLCs has made the thermal problem, even more, sever and therefore incurs more leakage energy consumption compared to conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose a runtime cache architecture called NIZCache. The core idea of NIZCache is to use the non-uniform distribution of the accesses, invalid lines, and zero-value lines in banks of last level cache for decreasing both dynamic and leakage energy. The proposed architecture that is based on non-uniform cache architectures (NUCA) disables cache banks that have low accesses and high invalid and zero lines and leads to high energy-efficiency. The Experimental results show that the proposed method improves the energy-delay product by about 17% on average under PARSEC benchmarks compared to previous work.

In this article, we present a convex optimization model to design a stacked hybrid memory system contains eDRAM and STT-RAM banks with minimum write energy consumption of STT-RAM memory banks and minimum refresh energy of eDRAM banks with efficient number of TSVs in embedded CMP. Our convex model optimizes numbers and placement of memory banks from different technologies on the memory layer and finding optimal number and optimal placement of TSVs while satisfy maximum Load on TSVs. Experimental results on PARSEC benchmark show that the proposed Architecture improves energy-delay product (EDP) by 51% on average.

In this paper a new methodology and implementation of an experimental infrared (IR) measurement technique for the thermal and electrothermal analysis of electronic circuits is presented. The electrothermal analysis is based on coupling a circuit simulator and IR thermography measurement through an application program interface that updates the temperature information in near-real time. This method is applied to study the performance of a power MOSFET circuit.

An infrared (IR) thermography measurement setup to capture the temperature distribution and power dissipation of the device under test is proposed in this paper. The system is based on a transparent oil heatsink which captures the thermal profile and run-time power dissipation from the device under test with a very fine degree of granularity. The proposed setup is used to perform the thermal analysis and power dissipation measurement of an Intel Dual Core E2180 processor. In addition, a three-dimensional finite element thermal model of the processor is developed to simulate the thermal properties of the processor. The results obtained using simulation efforts are compared to the experimental results from IR thermography.

This paper presents the generation and verification of a dynamic compact thermal model of electronic packages. The method is demonstrated for Ball Grid Array (BGA) package. The resulting RC network dynamic compact thermal model is optimized to diverse conditions typical to the application-specific environment. The accuracy of the model is found sufficient for thermal design purposes in terms of predicted junction temperature response and heat flux of the desired locations of the package.