This paper proposes a digital background calibration scheme for the compensation of the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. The proposed calibration method, called the piecewise multi-correlation estimation (PMCE) technique, injects two pseudo-random number (PN) sequences within two adjacent dither windows to extract gain coefficients. This method transforms the estimation of nonlinear gains into the estimation of two linear gains, thus achieving rapid convergence. The proposed calibration scheme does not result in the output swing degradation of the multiplying DAC (MDAC) due to dither injection. The required modification to analog circuits involves only three additional comparators and a capacitor for dither injection. Monte Carlo simulation results of a 14-bit 1.3GS/s pipelined ADC show that the average SFDR of the ADC is improved from 59.61 dB to 91.11 dB.

This paper presents a novel parallel convolution-self-attention neural network (PCSANN) based calibration scheme for Pipelined and Pipelined-SAR ADCs. Combining convolution neural network (CNN) and self-attention neural network (SANN), the proposed architecture jointly calibrates various nonlinearities in ADCs as a black box, including comparator offsets, inter-stage gain error (IGE), inter-stage nonlinearity, digital-to-analog converter (DAC) errors, memory effect (ME), etc. This proposed calibration scheme is validated with a fabricated 12-bit 150MSps pipelined ADC prototype and a fabricated 12-bit 750MSps pipelined-SAR ADC prototype. Measurement results show that the spurious-free dynamic range (SFDR) of the pipelined ADC is improved by 14.17dB from 64.98dB to 79.15dB, and the pipelined-SAR ADC achieves a 7.60dB improvement in SFDR from 63.00dB to 70.60dB.

This paper presents a novel calibration scheme for single-channel SAR, pipelined and pipelined-SAR ADCs using Kolmogorov–Arnold networks (KANs). In the proposed scheme, a multi-sample KAN (MS-KAN) is designed to realize nonlinear code synthesis (NLCS), achieving effective calibration for general nonlinear errors. The MS-KAN-based calibrator can be converted into an analytical expression, making the calibration process transparent, with stronger interpretability, predictability and reliability compared to previous neural network-based calibration algorithms, and assisting in the analysis of ADC nonidealities. Meanwhile, the proposed scheme achieves high calibration performance with low hardware overhead. The proposed scheme also requires much fewer training samples, thereby reducing the effort required for both chip testing and network training. The MS-KAN-based calibrator is verified with two silicon-proven ADCs, a 14-bit 1.3 GS/s pipelined ADC and a 10-bit 700MS/s SAR ADC. Measurement results show that SFDR is improved by 11.5 dB to 30.9 dB after calibration. The quantized calibrators are implemented on both FPGA and 28nm CMOS technology, where a piecewise polynomial (PWP) method is adopted to simplify the implementation of the calibrator. The post-layout simulation results show that the calibrator for the real-time calibration of the pipelined ADC consumes only 6.32 mW, while the calibrator for the SAR ADC consumes 2.42 mW.

This paper proposes a novel digital background calibration technique for interstage gain error (IGE) and gain nonlinearity in pipelined analog-to-digital converters (ADCs). Through the random switching of the multiplying digital-to-analog converter (MDAC) between two operating modes, two interstage residue curves are obtained. The IGE and the third-order gain nonlinearity are calibrated according to the distance and the geometric relationship between the two residue curves, respectively. For the proposed calibration scheme, the analog circuits require no modifications, except for the addition of several multiplexers and switches. The advantages of the proposed technique include a simple algorithm, fast convergence, and low power consumption. The simulation results show that the signal-to-noise and distortion ratio and spurious-free dynamic range of a 14-bit 1 Gsps pipelined ADC improve from 44.86 and 55.54 dB to 77.99 and 86.16 dB, respectively, after calibration. During the calibration process, the IGE and gain nonlinearity converge after 2.5 × 105and 2 × 105sampling cycles, respectively.

This article presents a new artificial neural network (ANN)-based calibration mechanism for analog-to-digital converters (ADCs). The proposed mechanism applies ANN to realize the bijective vector recovery mapping (VRM) for nonlinearity calibration and thus effectively suppresses both harmonic distortions and spurs. A new ANN-based calibrator is designed to calibrate both single-channel nonlinearity and interchannel mismatches and significantly improve the performance of ADCs. Through signal-fitting-based training process and noise adding, the proposed mechanism and calibrator can calibrate the general nonlinearity and mismatches of ADCs, including but not limited to the typical nonideality that conventional calibration techniques commonly concern (such as interstage gain error, digital-to-analog converter (DAC) error, and timing mismatch). For verification, an on-chip ANN-based calibrator is implemented in a 12-bit 600-MS/s four-channel time-interleaved (TI) ADC prototype. The measurement results show that signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.79 and 35.30 to 62.45 and 74.21 dB, respectively. Another off-chip ANN-based calibrator is applied to a commercial 12-bit 5.4-GS/s four-channel ADC, and the results show that the SNDR and SFDR are improved from 42.38 and 43.17 to 53.98 and 78.25 dB, respectively.

This paper presents a convolutional neural network (CNN) based error calibration scheme for pipelined ADC. The output of the pipelined ADC is taken as the input data of the network, and the network produces error compensation values. The network is applied in a 14-bit 1GSps pipelined ADC model with nonlinear errors including inter-stage gain error (IGE), DAC errors, thermal noise and sampling jitter for verification. The trained network scheme is verified with various types of signals including single-tone, dual-tone, amplitude modulation (AM) and frequency modulation (FM) signals. Simulation results show that, the SFDR and SNDR of the pipelined ADC are improved from 62.58dB and 58.82dB to 89.86dB and 66.66dB after calibration. Meanwhile, after calibration, the spurs of the dual-tone, AM and FM signals have been effectively suppressed.

This paper demonstrates a new neural-network-based calibration technique for inter-channel mismatches of time-interleaved ADCs. By providing with signal value and derivative value of each channel, the network could calibrate the gain mismatch, offset mismatch, and timing mismatch of TI-ADCs. By utilizing signal feature fitting, the ground truth for network training could be obtained without an accurate reference ADC nor a precise ADC error model. Simulation results show that the proposed calibration technique can increase the SFDR of a 14-bit 4Gsps TI-ADC from 32.77 dB to 91.71 dB for single-tone signals, and suppress the maximum spur from −48.51 dBFS to −101.23 dBFS for multi-tone signals. A hardware implementation resources estimation is also given in this paper.

This brief proposes a timing mismatch calibration for time-interleaved analog-to-digital converters (TI ADCs) with the novel parallel correlation derivative (PCD) technique and two-stage analog–digital hybrid compensation. The PCD technique could solve the frequency-relevant problem caused by low correlation derivative in the precise skew calculation. Besides, the compensation scheme with an analog coarse correction and then the all-digital fine correction is used to cover a larger normalized skew range and bandwidth with maintained calibration performance. Compared to previous works on timing mismatch calibration, this work has improved accuracy with a larger effective bandwidth and a larger skew calibration range. The technique is applied in a four-channel 14-bit 3 GS/s ADC model to verify its effectiveness. Simulation results show that it increases the SNDR and SFDR from 31.02 and 32.87 to 54.40 and 93.49 dB at${f}_{\text {in}}\,\,=\,\,0.99{f}_{s}$and maintains good performance in the first three Nyquist bands.

Power budget is an important power constraint provided to guarantee the thermal reliability of an integrated system. In this work, we present DBP, a distributed power budgeting method, for dark silicon many-core systems. In DBP, there are two new techniques proposed to bring accurate and optimized power budgets in a distributed way. First, a distributed active core locating technique is developed to find an active core distribution that leads to a high-power budget. Second, a distributed power budget computing technique is introduced which computes the power budget for each active core accurately. Experiments show DBP outperforms the state-of-the-art power budgeting methods’ thermal safe power (TSP) and greedy dynamic power (GDP) on many-core dark silicon systems by providing a high and accurate power budget with low overhead and good scalability.

Because the increasing power density is limited by the thermal constraint, multi-core integrated systems have stepped into the dark silicon era recently, meaning not all parts of the system can be powered on at the same time. Dark silicon effects are, especially severe for 3-D microprocessors due to the even higher power density caused by the stacked structures, which greatly limit the system performances. In this article, we propose a greedy based core-cache co-optimization algorithm to optimize the performance of 3-D microprocessors in dark silicon at runtime. The new method determines many runtime settings of the 3-D system on the fly, including the active core and cache bank positions, active cache bank number, and the voltage/frequency (V/f) level of each active core, which optimizes the performance of the 3-D microprocessor under thermal constraint. Because the core-cache settings are co-optimized in the 3-D space and the power budgets are computed dynamically according to the running state of the 3-D microprocessor, the new method leads to a higher system performance compared with the existing methods. Experiments on two 3-D microprocessors show the greedy-based core-cache co-optimization algorithm outperforms the state-of-the-art 3-D dark silicon microprocessor performance optimization method by achieving a higher processing throughput with guaranteed thermal safety.

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

Leakage power is becoming significant in new generation IC chips. As leakage power is nonlinearly related to temperature, it is challenging to manage the thermal behavior of today's multicore systems, since thermal management becomes a nonlinear control problem. In this paper, a new predictive dynamic thermal management (DTM) method with neural network thermal model is proposed to naturally consider the inherent nonlinearity between leakage and temperature. We start with analyzing the problems of using recurrent neural network (RNN) to build the nonlinear thermal model, and point out that there is exploding gradient induced long-term dependencies problem, leading to large model prediction errors. Based on this analysis, we further propose to use echo state network (ESN), which is a special type of RNN, as the leakage-aware nonlinear thermal model. We theoretically and experimentally show that ESN achieves much higher accuracy by completely avoiding the long-term dependencies problem. On top of this nonlinear ESN thermal model, we propose a novel model predictive control (MPC) scheme called ESN MPC, which uses iterative steps to find the optimal future power recommendations for thermal management. Being able to consider the leakage-temperature nonlinear effects and equipped with advanced control technique, the new method achieves an overall high quality temperature management with smooth and accurate temperature tracking. The experimental results show the new method outperforms the state-of-the-art leakage-aware multicore DTM method in both temperature management quality and computing overhead.

Temperature control of the new-generation integrated multicore system is challenging. This is because the leakage power, which is significant in modern systems, is nonlinearly related to temperature, resulting in a complex nonlinear control problem in thermal management. In this article, a new dynamic thermal management (DTM) method with compact piecewise linear (PWL) model based predictive control is proposed to solve the nonlinear control problem. First, a compact PWL thermal model, which takes dynamic power as input, is built by combining multiple local compact linear thermal models expanded at several Taylor expansion points. These local compact linear thermal models are obtained by sampling-based model order reduction with high accuracy. Their Taylor expansion points are selected by a systematic scheme, which exploits the thermal behavior property of the multicore chips. Based on the compact PWL thermal model, a new predictive control method is proposed to compute the future power recommendation for DTM. By approximating the nonlinearity accurately with the compact PWL thermal model and being equipped with predictive control technique, the new DTM achieves an overall high quality temperature management with smooth and accurate temperature tracking. Experimental results show that the new method outperforms the linear model predictive control based method and the echo state network based predictive thermal management method in temperature management quality with lower computing overhead.

A novel voltage comparator, termed an edge-race comparator (ERC), is proposed in this article. It compares the differential input voltage by generating two propagating edges in two inverter loops and by measuring the distance between the two edges. The two edges race with each other and the winner is finally determined. The comparator is low power and low noise and does not require high-voltage headroom. It can automatically adjust its noise, power consumption, and delay according to the input voltage, thereby saving significant energy and time in coarse comparisons and reducing the noise in fine comparisons (noise averaging is performed over a longer time in fine comparisons). It is well suited for low-power, high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) (SAR ADCs). Compared to a recently published edge-pursuit comparator (EPC), the proposed structure achieves 3.39 times faster speed at 1-mV input by using a novel configuration of two inverter loops with a distance measurement circuit. The energy consumption per comparison is reduced by 2.73 times at 1-mV input owing to the shorter required comparison time. Designed in a standard 40-nm CMOS process, the measurement results from an ADC show that the comparator energy at the LSB is reduced by 7.5 times, and the ADC sampling rate is increased by 3.85 times.

Performing thermal management on new generation IC chips is challenging. This is because the leakage power, which is significant in today's chips, is nonlinearly related to temperature, resulting in a complex nonlinear control problem in thermal management. In this paper, a new dynamic thermal management (DTM) method with piecewise linear (PWL) thermal model based predictive control is proposed to solve the nonlinear control problem. First, a PWL thermal model is built by combining multiple local linear thermal models expanded at several Taylor expansion points. These Taylor expansion points are carefully selected by a systematic scheme which exploits the thermal behavior property of the IC chips. Based on the PWL thermal model, a new predictive control method is proposed to compute the future power recommendation for DTM. By approximating the nonlinearity accurately with the PWL thermal model and being equipped with predictive control technique, the new DTM can achieve an overall high quality temperature management with smooth and accurate temperature tracking. Experimental results show the new method outperforms the linear model predictive control based method in temperature management quality with negligible computing overhead.

Dark silicon phenomenon is significant in today's multi/many-core systems manufactured using new generation technology. In order to enhance performance of dark silicon systems, power budget constrained dynamic optimizations are performed in various ways including dynamic voltage and frequency scaling (DVFS) and task scheduling. However, power budgets given by existing methods are generally over pessimistic, which greatly limit the capability of dynamic performance optimization methods. In order to resolve this problem, we propose a dynamic power budgeting method, called Greedy based Dynamic Power (GDP). Different from existing methods, which are steady state based and ignore active core distributions, GDP formulates the power budgeting problem as a thermal-constrained combinational power optimization problem. To efficiently solve this problem, we propose two new ideas: first, we transform the original power-optimization problem to an easier solving temperature-optimization problem; second, we employ a more efficient greedy based algorithm that finds a sub-optimal active core distribution which maximizes power budget. The new method can consider current temperature states and transient thermal effects, which were ignored by existing methods. Both theoretical studies and experimental results show that GDP outperforms existing methods by providing a higher and less pessimistic power budget with low computing cost and guaranteed thermal safety.

Accurate and fast reliability management is important for 3-D integrated circuits (3-D ICs) because of the severe on-chip thermal and reliability problems. However, due to the lack of stress information and difficulties in implementing management method for reliability, existing full-chip reliability management methods suffer from low management accuracy and high system performance degradation. In this paper, we propose a new stress and thermal aware reliability management method for 3-D ICs called STREAM. Unlike traditional methods which do not perform explicit stress analysis due to the large computing cost, STREAM employs an artificial neural network-based stress model to estimate stress accurately at runtime. In order to further improve the reliability management accuracy and improve the system performance, a lifetime estimator with lifetime banking technology and a specially designed lifetime model predictive control are integrated into the reliability management framework. Our numerical results show that STREAM performs the stress and thermal aware full-chip reliability management with both high accuracy and speed. It is able to boost the performance of 3-D ICs and outperforms the state-of-the-art 3-D IC reliability management method.

Heat dissipation and the related thermal-mechanical stress problems are the major obstacles in the development of the three-dimensional integrated circuit (3D IC). Reliability management techniques can be used to alleviate such problems and enhance the reliability of 3D IC. However, it is difficult to obtain the time-varying stress information at runtime, which limits the effectiveness of the reliability management. In this article, we propose a fast stress estimation method for runtime reliability management using artificial neural network (ANN). The new method builds ANN-based stress model by training offline using temperature and stress data. The ANN stress model is then used to estimate the important stress information, such as the maximum stress around each TSV, for reliability management at runtime. Since there are a variety of potential ANN structures to choose from for the ANN stress model, we analyze and test three ANN-based stress models with three major types of ANNs in this work: the normal ANN-based stress model, the ANN stress model with hand-crafted feature extraction, and the convolutional neural network–(CNN) based stress model. The structures of each ANN stress model and the functions of these structures in 3D IC stress estimation are demonstrated and explained. The new runtime stress estimation method is tested using the three ANN stress models with different layer configurations. Experiments show that the new method is able to estimate important stress information at extremely fast speed with good accuracy for runtime 3D IC reliability enhancement. Although all three ANN stress models show acceptable capabilities in runtime stress estimation, the CNN-based stress model achieves the best performance considering both stress estimation accuracy and computing overhead. Comparison with traditional method reveals that the new ANN-based stress estimation method is much more accurate with a slightly larger but still very small computing overhead.

This paper proposes a low-power low-cost on-chip digital background calibration for a pipelined ADC. This new redundant-stage calibration algorithm reduces the effect of quantization noise and can be applied for multiple stages; hence, it improves the calibration accuracy and is easily implemented fully on-chip with low power and low hardware cost. We realize the proposed calibration technique in a prototype 12-bit 250-MS/s pipelined ADC fabricated in a 55-nm technology. The measured results show that the prototype ADC, with an active area of 1310 gm × 510 gm, achieves an signal-to-noise-and-distortion ratio of 66.7 dB [effective number of bits (ENOB) = 10.8 bit] and consumes a total power of 85 mW with a sampling rate of 250 MS/s after applying our digital calibration, where the on-chip digital calibration circuit consumes only 5 mW and an active area of 360 gm × 510 gm.

Accurate and fast thermal estimation is important for the runtime thermal regulation of modern microprocessors due to excessive on-chip temperatures. However, due to the nonlinear relationship between the leakage power and temperature, full-chip thermal estimation methods suffer slow speed and scalability issue when the increasing static leakage power is considered. In this work, we propose a new fast leakage-aware full-chip thermal estimation method. Unlike traditional methods, which use iteration to handle the leakage-temperature nonlinearity dependency issue, the new method applies a dynamic linearization algorithm, which adaptively transforms the original nonlinear thermal model into a number of local linear thermal models. In order to further improve the thermal estimation efficiency, a specially-designed adaptive model order reduction method is integrated into the thermal estimation framework to generate local compact thermal models. Our numerical results show that the new method is able to accurately estimate full-chip transient temperature distribution by fully considering the nonlinear leakage-temperature dependency with fast speed. On different chips with core number ranging from 9 to 36, it achieved 85x to 589x speedup in average against traditional iteration based method, with average thermal estimation error to be around 0.2°C.

It is challenging to manage the thermal behavior of many-core microprocessors while still keeping them running at high performance since the control complexity increases as the core number increases. In this article, a novel hierarchical dynamic thermal management method is proposed to overcome this challenge. The new method employs model predictive control (MPC) with task migration and a DVFS scheme to ensure smooth control behavior and negligible computing performance sacrifice. In order to be scalable to many-core systems, the hierarchical control scheme is designed with two levels. At the lower level, the cores are spatially clustered into blocks, and local task migration is used to match current power distribution with the optimal distribution calculated by MPC. At the upper level, global task migration is used with the unmatched powers from the lower level. A modified iterative minimum cut algorithm is used to assist the task migration decision making if the power number is large at the upper level. Finally, DVFS is applied to regulate the remaining unmatched powers. Experiments show that the new method outperforms existing methods and is very scalable to manage many-core microprocessors with small performance degradation.

This paper reports a new scalable behavioral modeling technique for silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection structures using Verilog-A language. Accurate models were developed for various low-triggering voltage SCR ESD (LVSCR) protection structures implemented in a foundry 180nm RF process, which were validated by circuit simulation and ESD measurement.