This work presents a time register designed for time-domain signal processing, employing a delay line in a ring configuration topology combined with a digital counter to achieve a high dynamic range. The proposed architecture supports both addition and subtraction operations, offering a practical framework for understanding the implementation of such functionalities in the time domain. The register is capable of efficiently processing signals with durations ranging from picoseconds to milliseconds and demonstrating feasibility for physical implementation.

This paper introduces a novel time register for time-domain signal processing, utilizing a delay line within a ring configuration topology and a digital counter to achieve high dynamic range. The proposed design was implemented and simulated using the AMS 350 nm CMOS process and tested under nominal supply voltage of 3.3 V. Corner simulation, considering supply voltage, temperature, and process variations, demonstrated an error rate below 2% for inputs exceeding 50 ns. A key advantage of the proposed solution is that its range can be easily scaled by increasing the number of counter bits, while the layout area overhead introduced by the counter remains minimal. This is the first CMOS time register capable of efficiently processing signals from picoseconds to milliseconds, providing an output pulse equal to the input pulse, and being feasible for physical implementation.

This article presents a novel time-domain implementation of the second-order Goertzel frequency analyzer, which can be extended for use in infinite impulse response (IIR)/finite impulse response (FIR) filters. A set of time-domain arithmetic circuits, including a one-step time register (TR), time amplifier (TA), time adder, and unit delay operator (${z}^{-1}$), are introduced to overcome the limitations of conventional time-domain filters. The working principles and nonidealities of each block are analyzed and compared with the existing methods. The proposed filter is implemented in a 180-nm CMOS process with a 0.9-V supply voltage. The designed frequency analyzer is tunable to extract the amplitude and phase angle of signals up to 400 Hz. Simulation results, targeting a 280-Hz signal at a 19.88-kHz sampling frequency, demonstrate that the filter can detect the amplitude and phase of a voltage signal in the time domain with an error below 5%. The filter achieves a resolution of$76.7~\text {dBV/s}$, consumes less than$24~\mu \text {W}$of power, and the estimated silicon area is almost$0.828~\mathrm {mm}^{2}$.

This brief presents an open-loop current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) intended for ultralow power direct digitizing micro-sensors readout applications. The proposed highly linearized pseudo-differential${G}_{M}$-stage mitigates the harmonic distortions induced by the tune circuit to the nonlinear transfer characteristic of the voltage-controlled oscillator (VCO), and it improves the total SNDR considerably. The ADC is implemented in 180-nm CMOS and achieves a peak SFDR of 81.48 dB, THD of −76.8 dB, and SNDR of 70.9 dB (equivalent to 11.48 ENOB) over a 3.6 kHz bandwidth with a 110 mVPP input differential sinewave. A chopper is used for the input transconductance stage to mitigate the input-referred noise and its impact on output phase noise. The ADC consumes$20.3 \mu {\text {W}}$from a 1-V supply.