The pursuit of accurate diagnosis with good resolution is driven by yield learning during both early bring-up and production excursions. Unfortunately, fault callouts from diagnosis tools often render poor resolution that hinders the follow-up failure analysis. In this work, we propose a method that significantly improves diagnosis. By modeling the logic circuits under test as graphs, the method employs graph neural networks to determine each fault candidate from the diagnosis callout as either the true fault or the false candidate. This novel deep learning method mainly makes full use of circuitry topology with underlying structural information, which was largely ignored or insufficiently analyzed by previous approaches. Other contributions include the finding of the dependency among candidates that can be leveraged to improve diagnoses. Extensive experiments on various benchmark circuits including industrial designs demonstrate that the diagnostic resolution can be improved by 4.51× compared with a fault simulator-based diagnosis tool, and increased by 5.98× compared with one state-of-the-art commercial diagnosis tool. Moreover, experiments also reveal that our method can successfully identify 62.96% of true candidates that were originally not given high priority by the commercial tool (non top-scoring candidates). This means our method can rectify the existing commercial diagnosis for better characterizing failure Pareto, in addition to boost diagnostic resolution.

Failure diagnosis is a software-based, data-driven procedure. Collecting an excessive amount of fail data not only increases the overall test cost but can also potentially reduce diagnostic resolution. Thus, test-termination prediction is proposed to dynamically determine the appropriate failing test pattern to terminate testing, producing an amount of test data that is sufficient for an accurate diagnosis analysis. In this work, we describe a set of novel methods utilizing advanced machine learning techniques for efficient test-termination prediction. To implement this approach, we first generate images representing failing test responses from failure-log files. These images are then used to train a multi-layer convolutional neural network (CNN) incorporating a residual block. The trained CNN model leverages the images and known diagnostic results to determine the optimal test-termination strategy within the testing process, ensuring efficient and high-quality diagnosis. In addition to the integration of test response-to-image translation, our approach harnesses two cutting-edge learning strategies to enhance fail data and boost performance in subsequent tasks. The first strategy is transfer learning, which utilizes sample-label information from one circuit to guide the decision of whether to continue or stop testing for another circuit lacking labels. The second strategy involves the use of a generative deep model to generate fail data in the form of synthetic images. This technique increases the modeling effectiveness by expanding the volume of training samples. Experimental results conducted on actual failing chips and standard benchmarks validate that our proposed method surpasses existing approaches. Our method creates opportunities to harness the power of recent advances in machine learning for improving test and diagnosis efficiency.