Demo Data from EDBT 2026 / reviewers in the wild / expert
Binhao Bao
dblp:371/5308
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2024
0000-0002-8799-7194ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Storage systems · 100% | |
| Theoretical computer science
1 paper |
Coding theory · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
flash and SSD |
0.8 | 1 | 2024 | Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Storage systems › flash and SSD › flash memory
NAND flash |
0.8 | 1 | 2024 | Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Coding theory
error-correcting codes |
0.8 | 1 | 2024 | Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Coding theory › error-correcting codes › LDPC codes
LDPC decoding |
0.8 | 1 | 2024 | Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Methods — techniques the papers use, named apart from their topics
progressive LDPC decoding · 1.5adaptive granularity · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Adaptive Granularity Progressive LDPC Decoding for NAND Flash MemoryabstractProgressive low-density parity check (LDPC) code decoding has been widely used to correct increasing raw bit errors in NAND Flash memory. Once the decoding of a single logical page fails, the read-retry operation will reprocess at an increased read level with more accurate initial log-likelihood ratio (LLR) messages. However, the traditional progressive LDPC decodings with inappropriate read-level-increase granularities of read-retry operations introduce unnecessary flash read latency. By taking advantage of globally coupled LDPC (GC-LDPC) codes, an improved adaptive granularity progressive LDPC decoding (IAGPD) is proposed. This method can estimate the number of uncorrectable bit errors before each read-retry operation by detecting the unsatisfied local parity checks and general syndrome in the decoding failure. Then, it adaptively selects the optimal read-level-increase granularities for read-retry operations in the progressive LDPC decoding. Compared with the existing decoding methods, only by an extra 0.098% of the decoder area and two clock cycles, our method can reduce the flash read latency by up to 43%. And the solid-state drive (SSD) read response time on MQsim can be reduced by up to 32%. Binhao Bao, Qianhui Li, Wu Guan, Liping Liang 0001, Xin Qiu 0008 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |