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Tong-Yu Liu

dblp:371/8854 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2025
0000-0002-7795-4553ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Cloud and datacenter computing · 38% Performance modeling and evaluation · 33% Processor architecture and microarchitecture · 29%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cloud and datacenter computing
cluster resource management and scheduling
0.912025
Retrospecting Available CPU Resources: SMT-Aware Scheduling to Prevent SLA Violations in Data Centers · IEEE Trans. Parallel Distributed Syst. 2025
Processor architecture and microarchitecture › multithreading
simultaneous multithreading
0.912025
Retrospecting Available CPU Resources: SMT-Aware Scheduling to Prevent SLA Violations in Data Centers · IEEE Trans. Parallel Distributed Syst. 2025
Cloud and datacenter computing › cloud service management
service level agreement
0.312025
Retrospecting Available CPU Resources: SMT-Aware Scheduling to Prevent SLA Violations in Data Centers · IEEE Trans. Parallel Distributed Syst. 2025
Performance modeling and evaluation
workload characterization
0.212024
Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping · ACM Trans. Archit. Code Optim. 2024

Methods — techniques the papers use, named apart from their topics

data-driven CPU resource estimation · 0.9RCPU · 0.9sampling ratio optimization · 0.8adaptive grouping · 0.8
YearPublicationVenuePosition
2025 Retrospecting Available CPU Resources: SMT-Aware Scheduling to Prevent SLA Violations in Data Centers
abstract
The article focuses on an understudied yet fundamental problem: existing methods typically average the utilization of multiple hardware threads to evaluate the available CPU resources. However, the approach could underestimate the actual usage of the underlying physical core for Simultaneous Multi-Threading (SMT) processors, leading to an overestimation of remaining resources. The overestimation propagates from microarchitecture to operating systems and cloud schedulers, which may misguide scheduling decisions, exacerbate CPU overcommitment, and increase Service Level Agreement (SLA) violations. To address the potential overestimation problem, we propose an SMT-aware and purely data-driven approach namedRemaining CPU(RCPU) that reserves more CPU resources to restrict CPU overcommitment and prevent SLA violations. RCPU requires only a few modifications to the existing cloud infrastructures and can be scaled up to large data centers. Extensive evaluations in the data center proved that RCPU contributes to a reduction of SLA violations by 18% on average for 98% of all latency-sensitive applications. Under a benchmarking experiment, we prove that RCPU increases the accuracy by 69% in terms of Mean Absolute Error (MAE) compared to the state-of-the-art.
Haoyu Liao, Tong-Yu Liu, Jianmei Guo, Bo Huang 0002, Dingyu Yang, Jonathan Ding
IEEE Trans. Parallel Distributed Syst.2
2024 Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping
abstract
Collecting sufficient microarchitecture performance data is essential for performance evaluation and workload characterization. There are many events to be monitored in a modern processor while only a few hardware performance monitoring counters (PMCs) can be used, so multiplexing is commonly adopted. However, inefficiency commonly exists in state-of-the-art profiling tools when grouping events for multiplexing PMCs. It has the risk of inaccurate measurement and misleading analysis. Commercial tools can leverage PMCs, but they are closed source and only support their specified platforms. To this end, we propose an approach for efficient cross-platform microarchitecture performance measurement via adaptive grouping, aiming to improve the metrics’ sampling ratios. The approach generates event groups based on the number of available PMCs detected on arbitrary machines while avoiding the scheduling pitfall of Linux perf_event subsystem. We evaluate our approach with SPEC CPU 2017 on four mainstream x86-64 and AArch64 processors and conduct comparative analyses of efficiency with two other state-of-the-art tools, LIKWID and ARM Top-down Tool. The experimental results indicate that our approach gains around 50% improvement in the average sampling ratio of metrics without compromising the correctness and reliability.
Tong-Yu Liu, Jianmei Guo, Bo Huang 0002
ACM Trans. Archit. Code Optim.1