Accurate and efficient depth estimation from time-of-flight (ToF) LiDAR is essential for autonomous systems operating in real-world environments. However, traditional histogram-based depth estimation (HBDE) algorithms face fundamental limitations in balancing depth performance and computational cost, and they struggle under signal-induced pile-up distortion. While deep learning has shown promise, existing neural network-based methods rely on large models that are impractical for deployment on edge hardware. To bridge this critical gap, we propose a paradigm shift in histogram-based ToF estimation, reframing depth estimation from signal filtering to lightweight similarity learning. Instead of attempting to correct the distorted signal, our approach learns a specialized metric where the measure of similarity between the distorted histogram and a reference pulse is the temporal shift itself. The resulting 57.61 KB model, over 215.2 times smaller than state-of-the-art deep learning approaches, achieves real-time performance (106.27 fps) on an FPGA. It delivers superior accuracy across nearly all signal-noise conditions, including 2.21 cm RMSE at severe pile-up scenarios, significantly outperforming conventional methods while remaining practical for on-device deployment.

Advances in semiconductor scaling and integration have increased design complexity, concentrating valuable IP in single chips. Reverse engineering using high-resolution microscopy techniques, such as scanning electron microscopy (SEM) and transmission electron microscopy (TEM), enables detailed circuit analysis and extraction of layout-level information. At the same time, reliance on external foundries increases the risks of design information leakage. To address these challenges, we propose a Fast Post-Manufacturing Programmable Camouflaged (FP2C) Logic Family, which consists of physically identical logic structures that are activated by applying a post-programming code (PC) after fabrication. The proposed FP2C logic-embedded Flip-Flop (FP2C logic-eFF) was implemented using a 28nm CMOS process, achieving a 67% reduction in cell area compared to prior Post-Manufacturing Programmed Threshold Voltage Defined (PMP-TVD) logic cells on the same technology node. Furthermore, this paper presents a systematic design methodology that integrates FP2C logic-eFF into an EDA tool-based digital circuit design flow. This enables FP2C logic to move beyond prior camouflaged logic that was limited to full-custom arithmetic unit implementations, and extend to complex digital IPs. To validate its feasibility, an AES module was designed and its functionality was verified through SPICE simulation, thereby demonstrating the applicability of FP2C logic to complex digital modules.

Masked diffusion models have demonstrated competitive results on various tasks including language generation. However, due to its iterative refinement process, the inference is often bottlenecked by slow and static sampling speed. To overcome this problem, we introduce `KL-Adaptive Stability Sampling' (KLASS), a fast yet effective sampling method that exploits token-level KL divergence to identify stable, high-confidence predictions. By unmasking multiple tokens in each iteration without any additional model training, our approach speeds up generation significantly while maintaining sample quality. On reasoning benchmarks, KLASS achieves up to $2.78\times$ wall-clock speedups while improving performance over standard greedy decoding, attaining state-of-the-art results among diffusion-based samplers. We further validate KLASS across diverse domains, including text, image, and molecular generation, showing its effectiveness as a broadly applicable sampler across different models.