Parameter tuning for multi-FPGA partitioning algorithms represents a bottleneck in modern chip emulation and verification workflows. Current multilevel partitioning tools require manual configuration of various parameters, where each evaluation can take tens of seconds to minutes, making exhaustive search impractical and expert-driven tuning both time-consuming and suboptimal. To automate this process, we propose a preference-guided Bayesian optimization framework specifically designed for industrial FPGA partitioning parameter tuning under limited evaluation budgets. Our approach maximizes the minimum timing slack by incorporating domain-specific insights: we exploit the strong correlation between cutsize and timing performance through a priority-based ranking scheme that guides a pairwise Gaussian process to learn configuration preferences. Additionally, we introduce a kernel input transformation that properly handles the mixed discrete-continuous parameter space typical in EDA tools. Our method converges faster with fewer evaluations and achieves the best timing slack in 60–70% of cases on industrial circuit benchmarks compared to existing methods including standard Bayesian optimization, quasi-random sampling, and state-of-the-art preference learning techniques. The proposed framework reduces parameter tuning from days of manual effort to hours of automated optimization, offering practitioners a deployment-ready solution that improves both design quality and engineering productivity.

Hypergraph partitioning is a fundamental combinatorial optimization problem with critical applications in VLSI design. While recent deep learning based approaches have shown promise for this problem, they rely on graph neural networks (GNNs) that require transforming hypergraphs into normal graphs, thereby losing the high-order relationships in hypergraph structures. In this work, we propose a novel framework that directly utilizes hypergraph neural networks (HGNNs) to exploit the high-order interactions in hypergraphs. We develop an efficient normalized cut loss computation algorithm optimized for GPU training and apply randomized matrix decomposition techniques to significantly accelerate the eigenvector computation required for node feature extraction without sacrificing quality. To address the scarcity of open-source hypergraph data, we release a comprehensive dataset with 164 VLSI hypergraphs collected from various EDA contests and benchmarks. Extensive experiments on the ISPD98 and ISPD05 benchmarks demonstrate that our method achieves superior partitioning quality compared to state-of-the-art approaches, including multilevel methods (hMETIS), spectral methods (SpecPart, K-SpecPart), and recent deep learning based approaches (MedPart, GenPart). Furthermore, training on our expanded dataset yields additional performance gains, validating the framework’s ability to leverage larger training data effectively.

As the scale of integrated circuit (IC) design continues to expand, the multi-FPGA system (MFS) is widely employed for logic emulation and simulation acceleration which ensures the functional correctness of logic circuits. During this process, circuit partitioning becomes a dispensable step. In this work, we address the hypergraph modeling techniques for the MFS-orientated circuit partitioning. Firstly, an efficient adaptive flattening algorithm considering multi-dimensional resource constraints and based on dynamic programming (DP) is proposed. Then, a parallel algorithm for clock modeling is proposed. With them, an efficient tool of hypergraph modeling is developed. Experiments on industrial benchmarks with up to sixty million cells have validated the efficiency and correctness of the proposed techniques. The results also demonstrate the benefit of the adaptive flattening to the subsequent hypergraph partitioning, and the significant acceleration effects of the proposed DP-based adaptive flattening and the parallel clock modeling algorithms.

Balanced hypergraph partitioning is a fundamental problem in applications like VLSI design, high-performance computing, etc. Nowadays, large-scale hypergraphs become more common due to the increasing complexity of modern systems. Thus, fast and high-quality deterministic partitioning algorithms are largely in demand. Regarding the quality of partitioning, balance is a critical concern when the number of partitions increases. In this paper, we propose BlasPart, a deterministic parallel algorithm for balanced large-scale hypergraph partitioning. BlasPart leverages a recursive multilevel bisection framework to achieve high-quality partitions while ensuring deterministic outcomes. A level-dependent balance constraint is also proposed to further improve the efficiency and effectiveness of the proposed partitioner. Extensive experiments, with comparisons to the state-of-the-art partitioners (hMETIS, BiPart, and Mt-KaHyParSDet), demonstrate that BlasPart achieves better balance and scalability while maintaining competitive partitioning quality and efficiency. BlasPart runs $3.33 \times$ faster than Mt-KaHyPar-SDet on average for a 4096-way partitioning task on six benchmarks.

Logic verification becomes more and more important for the design of large-scale digital integrated circuits (ICs). This makes FPGA-based hardware emulation an imperative step in the design flow, and how to effectively partition and map the circuit netlist into the multi-FPGA system (MFS) for emulation is of concern. In this paper, we present EasyPart, an effective and comprehensive hypergraph partitioner for the FPGA-based hardware emulation. EasyPart can handle the practical constraints in the MFS for logic emulation and includes novel techniques for pursuing minimum hop during topology-driven partitioning and treating the interconnection constraints. We have evaluated EasyPart against state-of-the-art partitioners on public benchmarks. The results show that EasyPart can reduce the cutsize with a comparable or shorter runtime. EasyPart is capable of finding non-hop solutions with better robustness and performance compared to previous work. It also achieves significant improvements in terms of time division multiplexing (TDM) ratio and maximum hop when tested on industrial cases.

With the rapid development of electronic payment, risks in large-scale financial transaction networks are persistently arising. One important problem is how to use the transaction data to detect sellers who do fraudulent trades on the online platform. This paper analyzes three attributes of the transaction flow: money (what), time (when), region (where), and summarizes corresponding characteristics among fraudulent sellers. Based on this, we propose an unsupervised anomaly detection algorithm: W3Detector. It processes the raw data with a new sequence discretization method and uses statistical tools to convert data indicators into information value. With the minimum description length principle, we finally filter out the suspicious sellers. The algorithm is not affected by factors such as unit or range of the attributes, and is highly flexible and scalable. After running on three real-world transaction datasets collected from WeChat Pay, W3Detector has show significantly better performance than the baseline methods of anomaly detection, with weighted accuraccy (WACC) increased by 1.13X and F-score increased by 0.105 on average, and the recall value over 60%.