Demo Data from EDBT 2026 / reviewers in the wild / expert
Emily Tucker
dblp:372/1865
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2025
0009-0002-1447-5683ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
High-performance computing · 82% Electronic design automation · 18% | |
| Theoretical computer science
1 paper |
Mathematical optimization · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Program verification · 100% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
High-performance computing
performance optimization |
0.9 | 1 | 2025 | Modular Construction and Optimization of the UZP Sparse Format for SpMV on CPUs · Proc. ACM Program. Lang. 2025 |
High-performance computing
sparse linear algebra |
0.9 | 1 | 2025 | Modular Construction and Optimization of the UZP Sparse Format for SpMV on CPUs · Proc. ACM Program. Lang. 2025 |
High-performance computing › sparse linear algebra
sparse matrix storage format |
0.9 | 1 | 2025 | Modular Construction and Optimization of the UZP Sparse Format for SpMV on CPUs · Proc. ACM Program. Lang. 2025 |
High-performance computing › sparse linear algebra › sparse matrix computation
sparse matrix-vector multiplication |
0.9 | 1 | 2025 | Modular Construction and Optimization of the UZP Sparse Format for SpMV on CPUs · Proc. ACM Program. Lang. 2025 |
Electronic design automation
high-level synthesis |
0.8 | 1 | 2024 | Formal Verification of Source-to-Source Transformations for HLS · FPGA 2024 |
Program verification › equivalence checking
semantic equivalence checking |
0.2 | 1 | 2024 | Formal Verification of Source-to-Source Transformations for HLS · FPGA 2024 |
Methods — techniques the papers use, named apart from their topics
polyhedral abstraction · 1.7integer lattice · 1.7symbolic analysis · 1.5concrete interpretation · 1.5abstract interpretation · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Modular Construction and Optimization of the UZP Sparse Format for SpMV on CPUsabstractSparse data structures are ubiquitous in modern computing, and numerous formats have been designed to represent them. These formats may exploit specific sparsity patterns, aiming to achieve higher performance for key numerical computations than more general-purpose formats such as CSR and COO. In this work presents UZP, a new sparse format based on polyhedral sets of integer points. UZP is a flexible format that subsumes CSR, COO, DIA, BCSR, etc., by raising them to a common mathematical abstraction: a union of integer polyhedra, each intersected with an affine lattice. We present a modular approach to building and optimizing UZP: it captures equivalence classes for the sparse structure, enabling the tuning of the representation for target-specific and application-specific performance considerations. UZP is built from any input sparse structure using integer coordinates, and is interoperable with existing software using CSR and COO data layouts. We provide detailed performance evaluation of UZP on 200+ matrices from SuiteSparse, demonstrating how simple and mostly unoptimized generic executors for UZP can already achieve solid performance by exploiting 𝒵-polyhedra structures. Alonso Rodríguez-Iglesias, Santoshkumar T. Tongli, Emily Tucker, Louis-Noël Pouchet, Gabriel Rodríguez 0001, Juan Touriño |
Proc. ACM Program. Lang. | 3 |
| 2024 | Formal Verification of Source-to-Source Transformations for HLSabstractHigh-level synthesis (HLS) can greatly facilitate the description of complex hardware implementations, by raising the level of abstraction up to a classical imperative language such as C/C++, usually augmented with vendor-specific pragmas and APIs. Despite productivity improvements, attaining high performance for the final design remains a challenge, and higher-level tools like source-to-source compilers have been developed to generate programs targeting HLS toolchains. These tools may generate highly complex HLS-ready C/C++ code, reducing the programming effort and enabling critical optimizations. However, whether these HLS-friendly programs are produced by a human or a tool, validating their correctness or exposing bugs otherwise remains a fundamental challenge. In this work we target the problem of efficiently checking the semantics equivalence between two programs written in C/C++ as a means to ensuring the correctness of the description provided to the HLS toolchain, by proving an optimized code version fully preserves the semantics of the unoptimized one. We introduce a novel formal verification approach that combines concrete and abstract interpretation with a hybrid symbolic analysis. Notably, our approach is mostly agnostic to how control-flow, data storage, and dataflow are implemented in the two programs. It can prove equivalence under complex bufferization and loop/syntax transformations, for a rich class of programs with statically interpretable control-flow. We present our techniques and their complete end-to-end implementation, demonstrating how our system can verify the correctness of highly complex programs generated by source-to-source compilers for HLS, and detect bugs that may elude co-simulation. Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez 0001, Zhiru Zhang |
FPGA | 2 |