EDBT 2026 Demo / reviewers in the wild / expert
Vincent Fu
dblp:372/9233
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0002-5058-7201ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 87% Processor architecture and microarchitecture · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design space exploration |
0.9 | 1 | 2025 | High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian Optimization · DAC 2025 |
Electronic design automation › design space exploration
microarchitecture design space exploration |
0.9 | 1 | 2025 | High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian Optimization · DAC 2025 |
Processor architecture and microarchitecture
multicore design |
0.3 | 1 | 2025 | High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian Optimization · DAC 2025 |
Methods — techniques the papers use, named apart from their topics
multi-objective optimization · 0.9bayesian optimization · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian OptimizationabstractThe emergence of new applications in high-performance computing is driving the need for more efficient computing machines. As supercomputer architectures become increasingly complex, the combinatorial explosion of design spaces and the time-consuming nature of design simulations lead to challenging design space exploration problems. This work introduces an automated search framework to achieve power-performance-area efficient Arm Neoverse V1 processor designs. Based on multi-objective Bayesian optimization, we propose a new exploration algorithm named SEBO by enhancing the three main stages of the optimization. Experimental results show that SEBO can not only compete with the top state-of-the-art baseline algorithms, but also outperforms them in terms of the quality and diversity of the returned Pareto-optimal designs. Vincent Fu, Mohamed Benazouz, Lilia Zaourar, Alix Munier Kordon |
DAC | 1 |