Pursuit of energy efficiency and accuracy in intelligent edge devices drives emerging non-volatile memories (NVM) developing more advanced computing-in-memory (CIM) architectures. The application of high performance magnetoresistive random-access memory (MRAM) in CIM has been limited due to its inherent non-ideal characteristics such as low resistance, low switching ratio, high area overhead and low accuracy. In this work, we introduce an innovative weighted two-transistor-one-MTJ (W-2T1R) VC-SOT-MRAM CIM macro that addresses these challenges with: 1) a novel 2T1R cell with high TMR; 2) an excellent approach to assign multi-bit array weight and the redundancy sub-track for linear promotion; 3) a bitwise input sparsity dataflow and architecture to improve energy and latency. Our proposal, excels at high linear computing, with energy efficiencies of 105.5 TOPS/W, area efficiency of 0.73 TOPS/mm2, throughput of 7.2 TOPS and classification accuracy of 91.46% on CIFAR-10 dataset for configurations comprising 6-bit input, 3-bit weight and 6-bit output on VGG-8 model.

The combination of computing-in-memory (CIM) architecture and emerging non-volatile memory (NVM) is considered as a promising alternative for low-power electronics. Among different emerging NVMs, the insufficient conductance level of magnetoresistive random-access memory (MRAM) is a serious limitation to introduce its high performance into analogue CIM architecture. In this paper, we propose a probabilistic binary neural networks(PBNN) hardware based on voltage-controlled spin-orbit torque MRAM (VC-SOT-MRAM), which employs 2T2MTJ sub-tracks integrated of the probabilistic switching MTJs to achieve the bit-wise weights sampling and activation. Selective writing is discussed to co-optimized. A pipeline readout circuit with hybrid dynamic reference was suggested to improve the precision and throughput. In addition, a weight mapping method is applied for multi-tracks computing in parallel and kernel duplicating to improve the efficiency. Our proposal, simulated in 28 nm technology, achievean energy efficiency of 312.5 bTOPS/W, throughput of 527.3 bGOPS, accuracies of >90% on MNIST with more acceleration (58×), less resource requirement (32×) and high robust row-parallel computing.

The current Internet makes forwarding decisions based on only destination addresses, leading to a prevalence of IP source address spoofing. To mitigate the risks posed by IP spoofing, Source Address Validation in Intra-domain and Interdomain Networks (SAVNET) has been recently proposed and become a hot topic in both academia and industry. While all network equipment can not be upgraded to support SAVNET during one night, incremental deployment is needed for network operators. However, SAVNET can not defend against all spoofing attacks under partial deployment. Thus, we need to carefully choose nodes to be deployed, to improve incentive benefits during incremental deployment. In this paper, we formulate the incremental problem and prove that the problem is NP-Complete. To efficiently solve the problem, we propose a heuristic deployment scheme named SOID (SAV protocol optimized incremental deployment). The intuitive idea of SOID is using the sink-tree to get the detectable flow sets of each router. Then, it selects the routers which have the maximum total weight during each iteration. To evaluate the performance of the proposed algorithm, we conduct comprehensive simulations with generated and real topologies. The simulation results show that SOID performs much better compared with traditional schemes, such as random deployment and minimum vertex cover algorithms, with a manageable overhead.