Deep neural networks (DNNs) have achieved remarkable success in various domains. However, their deployment on resource-constrained devices and in ultra-low-latency scenarios remains challenging due to their substantial computational and memory requirements. This paper proposes leveraging the low-dimensional computing (LDC) classifier, a low-dimensional variant of the vector symbolic architecture (VSA) classifier, as a lightweight alternative to DNNs. We introduce VSALUT, an open-source framework for implementing LDC on FPGAs. VSALUT employs a lookup table (LUT)-based architecture, an approximate encoding scheme to replace complex adders, a pruning strategy to reduce the model’s size, and a pipelining technique to maximize performance and resource efficiency. Evaluation on five datasets, commonly used to evaluate ultra-low latency architectures, demonstrates that VSALUT achieves significant hardware size and latency reductions over existing LDC, high-dimensional VSA, and LUT-based DNNs. This work establishes a promising new research direction for ultra-low-latency, lightweight inference on FPGAs using LDC.

Classification tasks on ultra-lightweight devices demand devices that are resource-constrained and deliver swift responses. Binary Vector Symbolic Architecture (VSA) is a promising approach due to its minimal memory requirements and fast execution times compared to traditional machine learning (ML) methods. Nonetheless, binary VSA’s practicality is limited by its inferior inference performance and a design that prioritizes algorithmic over hardware optimization. This paper introduces UniVSA, a co-optimized binary VSA framework for both algorithm and hardware. UniVSA not only significantly enhances inference accuracy beyond current state-of-the-art binary VSA models but also reduces memory footprints. It incorporates novel, lightweight modules and design flow tailored for optimal hardware performance. Experimental results show that UniVSA surpasses traditional ML methods in terms of performance on resource-limited devices, achieving smaller memory usage, lower latency, reduced resource demand, and decreased power consumption.

The run-time electromagnetic (EM) emanation of microprocessors presents a side-channel that leaks the confidentiality of the applications running on them. Many recent works have demonstrated successful attacks leveraging such side-channels to extract the confidentiality of diverse applications, such as the key of cryptographic algorithms and the hyperparameter of neural network models. This paper proposes ShuffleV, a microarchitecture defense strategy against EM Side-Channel Attacks (SCAs). ShuffleV adopts the moving target defense (MTD) philosophy, by integrating hardware units to randomly shuffle the execution order of program instructions and optionally insert dummy instructions, to nullify the statistical observation by attackers across repetitive runs. We build ShuffleV on the open-source RISC-V core and provide six design options, to suit different application scenarios. To enable rapid evaluation, we develop a ShuffleV simulator that can help users to (1) simulate the performance overhead for each design option and (2) generate an execution trace to validate the randomness of execution on their workload. We implement ShuffleV on a Xilinx PYNQ-Z2 FPGA and validate its performance with two representative victim applications against EM SCAs, AES encryption, and neural network inference. The experimental results demonstrate that ShuffleV can provide automatic protection for these applications, without any user intervention or software modification.

Artificial intelligence (AI) on tiny edge devices has become feasible thanks to the emergence of high-performance microcontrollers (MCUs) and lightweight machine learning (ML) models. Nevertheless, the cost and power consumption of these MCUs and the computation requirements of these ML algorithms still present barriers that prevent the widespread inclusion of AI functionality on smaller, cheaper, and lower-power devices. Thus, there is an urgent need for a more efficient ML algorithm and implementation strategy suitable for lower-end MCUs.

This paper introduces ALLI/O Diagram, an action-based visual programming language for embedded system programming used by the ALLI/O IDE. We illustrate the practicality of ALLI/O Diagram with various design examples and evaluate it against block-based, event-based, device-based, and state-based programming approaches in terms of programming effort, readability, and portability of the result programs. These results demonstrate that our proposed ALLI/O Diagram is the most compact, expressive, and portable across different hardware models. We open source the ALLI/O Diagram and all example programs at https://allio.build.