Demo Data from EDBT 2026 / reviewers in the wild / expert
Yuanqiu Lv
dblp:374/4392
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2025
0009-0007-7735-7031ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 61% GPUs and heterogeneous computing · 39% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › cache management
cache contention mitigation |
0.8 | 1 | 2024 | ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
GPUs and heterogeneous computing › GPU cache
GPU cache architecture |
0.8 | 1 | 2024 | ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Memory systems › cache design
shared l1 cache |
0.8 | 1 | 2024 | ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
GPUs and heterogeneous computing › GPU scheduling
GPU thread scheduling |
0.2 | 1 | 2024 | ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024 |
Methods — techniques the papers use, named apart from their topics
two-level thread-block scheduling · 0.8aggregated tag array · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Swift-Sim: A Modular and Hybrid GPU Architecture Simulation FrameworkabstractSimulation tools are critical for architects to quickly estimate the impact of aggressive new features of GPU architecture. Existing cycle-accurate GPU simulators are typically cumbersome and slow to run. We observe that it is time-consuming and unnecessary for cycle-accurate GPU simulators to perform detailed simulations for the entire GPU when exploring the design space of specific components. This paper proposes Swift-Sim, a modular and hybrid GPU simulation framework. With a highly modular design, our framework can choose appropriate modeling approaches for each component according to requirements. For components of interest to architects, we use cycle-accurate simulation to evaluate new GPU architectures. For other components, we use analytical modeling, which accelerates simulation speed with only minor and acceptable degradation in overall accuracy. Based on this simulation framework, we present two working examples of hybrid modeling that simulate the ALU pipeline and memory accesses using analytical models. We further implement two GPU performance simulators with different levels of simplification based on Swift-Sim and evaluate them using configurations from real GPUs. The results show that the two simulators achieve an 82.6x and 211.2x geometric mean speedup compared to Accel-Sim with insignificant accuracy degradation, Xiangrong Xu 0002, Yuanqiu Lv, Liang Wang 0020, Limin Xiao 0001, Runnan Shen, Jinquan Wang |
DATE | 2 |
| 2025 | Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache
Xiangrong Xu 0002, Liang Wang 0020, Limin Xiao 0001, Lei Liu 0037, Yuanqiu Lv, Xilong Xie, Xiaojian Liao |
J. Syst. Archit. | 6 |
| 2024 | ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag ArrayabstractTo fully exploit the locality of GPU applications, the GPU shared L1 cache architecture, which shares L1 cache among multiple GPU cores, is a promising architecture while still suffering from high resource contentions. We present a GPU shared L1 cache architecture with an aggregated tag array that minimizes the L1 cache contentions and takes full advantage of inter-core locality. The key idea is to decouple and aggregate the tag arrays of multiple L1 caches so that the cache requests can be compared with all tag arrays in parallel to probe the replicated data in other caches. The GPU caches are only accessed by other GPU cores when replicated data exists, filtering out unnecessary cache accesses that cause high resource contentions. We also develop a two-level thread-block scheduling policy adapted for the shared L1 cache architecture to maximize the available locality. The experimental results show that GPU performance can be improved by 14.5% on average for applications with a high inter-core locality. Xiangrong Xu 0002, Liang Wang 0020, Limin Xiao 0001, Lei Liu 0037, Yuanqiu Lv, Xilong Xie, Hao Liu 0107 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |