Logic locking is a widely adopted hardware obfuscation technique which can be further sub-categorised into static and dynamic approaches based on the nature of the employed key. Besides being susceptible to SAT and fault injection attacks, static logic locking is vulnerable to widespread compromise from a single key exposure or device breach. On the other hand, dynamic logic locking introduces complexities in resource utilisation, key management, design, and adaptability. In this work, we provide a comprehensive and up-to-date overview of existing IP Obfuscation techniques, highlighting their strengths, and potential vulnerabilities. We also propose, a hybrid logic locking technique that capitalises on the positive attributes of both static and dynamic logic locking methodologies while minimising their inherent limitations. An initial proof-of-concept implementation/simulation has been performed on the Xilinx SP605 FPGA development board. The suggested transient key logic locking scheme is applicable to all type of IPs.

Using correct design metrics and understanding the limitations of the underlying technology is critical to developing effective scheduling algorithms. Unfortunately, existing scheduling techniques used incorrect metrics and hadun-realisticassumptions for fair scheduling of multi-tenant FPGAs where each tenant is aimed to share approximately the same number of resources both spatially (in space) and temporally (in time).This paper proposes an improved fair scheduling algorithm that fixes earlier issues with metrics and assumptions for ‘fair’ multi-tenant FPGA use. Specifically, we claim three improvements. First, we consider both spatial and temporal aspects to provide spatiotemporal fairness—this improves a recent prior work that assumed all tasks would have the same latency. Second, we add the energy dimension to fairness: by calibrating the scheduling decision intervals and including their energy overhead, our algorithm offers trading off energy efficiency for fairness. Third, we consider previously ignored facts about FPGA multi-tenancy, such as the existence of heterogeneous regions and the inflexibility of run-time merging/splitting of partially reconfigurable regions.We develop and evaluate our improved fair scheduling algorithm with these three enhancements. Inspired by the Greek goddess of law and personification of justice, we name our fair scheduling solution THEMIS:Time,Heterogeneity, andEnergyMindedScheduling.We implemented our solution on Xilinx Zedboard XC7Z020 with real hardware workloads and used real measurements on the FPGA to quantify the savings of our approach. Compared to previous algorithms, our improved scheduling algorithm enhances fairness between 24.2–98.4% and allows a trade-off between 55.3× in energy vs. 69.3× in fairness. The paper thus informs cloud providers about future scheduling optimizations for fairness with related challenges and opportunities.