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Mengjia Dai

dblp:375/1334 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0002-7347-5117ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 56% Electronic design automation · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
high-level synthesis
0.812024
Allo: A Programming Model for Composable Accelerator Design · Proc. ACM Program. Lang. 2024
Hardware accelerators and domain-specific architectures › spatial architecture
spatial accelerator
0.812024
Allo: A Programming Model for Composable Accelerator Design · Proc. ACM Program. Lang. 2024
Hardware accelerators and domain-specific architectures
spatial architecture
0.212024
Allo: A Programming Model for Composable Accelerator Design · Proc. ACM Program. Lang. 2024

Methods — techniques the papers use, named apart from their topics

type-safe composition · 0.8high-level synthesis · 0.8
YearPublicationVenuePosition
2024 Allo: A Programming Model for Composable Accelerator Design
abstract
Special-purpose hardware accelerators are increasingly pivotal for sustaining performance improvements in emerging applications, especially as the benefits of technology scaling continue to diminish. However, designers currently lack effective tools and methodologies to construct complex, high-performance accelerator architectures in a productive manner. Existing high-level synthesis (HLS) tools often require intrusive sourcelevel changes to attain satisfactory quality of results. Despite the introduction of several new accelerator design languages (ADLs) aiming to enhance or replace HLS, their advantages are more evident in relatively simple applications with a single kernel. Existing ADLs prove less effective for realistic hierarchical designs with multiple kernels, even if the design hierarchy is flattened. In this paper, we introduce Allo, a composable programming model for efficient spatial accelerator design. Allo decouples hardware customizations, including compute, memory, communication, and data type from algorithm specification, and encapsulates them as a set of customization primitives. Allo preserves the hierarchical structure of an input program by combining customizations from different functions in a bottomup, type-safe manner. This approach facilitates holistic optimizations that span across function boundaries. We conduct comprehensive experiments on commonly-used HLS benchmarks and several realistic deep learning models. Our evaluation shows that Allo can outperform state-of-the-art HLS tools and ADLs on all test cases in the PolyBench. For the GPT2 model, the inference latency of the Allo generated accelerator is 1.7× faster than the NVIDIA A100 GPU with 5.4× higher energy efficiency, demonstrating the capability of Allo to handle large-scale designs.
Hongzheng Chen, Niansong Zhang, Shaojie Xiang, Zhichen Zeng 0002, Mengjia Dai, Zhiru Zhang
Proc. ACM Program. Lang.5