In this paper, we propose AMS-IO-Agent, a domain-specialized LLM-based agent for structure-aware input/output (I/O) subsystem generation in analog and mixed-signal (AMS) integrated circuits (ICs). The central contribution of this work is a framework that connects natural language design intent with industrial-level AMS IC design deliverables. AMS-IO-Agent integrates two key capabilities: (1) a structured domain knowledge base that captures reusable constraints and design conventions; (2) design intent structuring, which converts ambiguous user intent into verifiable logic steps using JSON and Python as intermediate formats. We further introduce AMS-IO-Bench, a benchmark for wirebond-packaged AMS I/O ring automation. On this benchmark, AMS-IO-Agent achieves over 70% DRC+LVS pass rate and reduces design turnaround time from hours to minutes, outperforming the baseline LLM. Furthermore, an agent-generated I/O ring was fabricated and validated in a 28 nm CMOS tape-out, demonstrating the practical effectiveness of the approach in real AMS IC design flows. To our knowledge, this is the first reported human-agent collaborative AMS IC design in which an LLM-based agent completes a nontrivial subtask with outputs directly used in silicon.

This paper presents a two-channel time-interleaved (TI) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with wide bandwidth, high resolution, and low power consumption. A shared loop filter realizes residue filtering between interleaved channels by midway feedback. The error feedback-cascaded integrator feedforward (EF-CIFF) loop filter architecture is adopted to achieve 3rd-order noise shaping with only one residue amplifier. A ring buffer is adopted to provide accurate gain by forming an inner feedback loop. PVT robust biasing and split current source architecture make the ring buffer immune to PVT variation and VCMmismatch. A prototype ADC in 28nm CMOS achieves 62.0 dB SNDR over 75 MHz bandwidth and consumes 5.9 mW, leading to a FoMs of 163 dB.

This paper introduces a hierarchical compilation approach for multi-channel reconfigurable analog-to-digital converter (ADC) systems, motivated by the need for highly flexible and scalable solutions in programmable converter arrays (PCAs). Unlike existing methods that mainly rely on manual circuitlevel adjustments with high complexity, limited scalability, and low flexibility, this method provides a structured and scalable hierarchical mapping scheme. This facilitates flexible and efficient configuration by integrating software and hardware design, making it highly suitable for automation and future expansion. It paves the way for the automatic synthesis, optimization and future expansion of PCAs.

This live demonstration presents a highly programmable analog-to-digital converter (ADC). The ADC is composed of an array of conversion blocks, each of which can be individually programmed. These conversion blocks can collaborate through a flexible bus system to achieve a wide range of functionalities and performance coverage. An interactive online programming system based on Matlab intuitively demonstrates how the ADC chip can be easily programmed. Additionally, the system includes a design rule check function to ensure programming validity, and a simulator to predict the actual performance. The system showcases an ADC performance range of MHz to GHz bandwidth and 30dB to 80dB SNDR.

This work presents a new analog-to-digital converter (ADC) architecture named programmable converter array (PCA) for multi-standard signal acquisition. Unlike prior reconfigurable ADCs that are mainly configured at the circuit level, PCA is highly flexible at the architecture level and can process multiple input signals simultaneously for mode concurrency. The elemental units in the converter array are Conversion Blocks (CBs) based on successive approximation register (SAR) ADCs. Multiple CBs can interleave or run synergically through a bus system to form sophisticated architectures. Fabricated in 28nm CMOS, the prototype converter array can be configured as over 16 modes, with an SNDR range from 30dB to 82dB and an aggregate bandwidth from sub-MHz to 1000MHz. The prototype achieves a peak Schreier figure of merit (FoMs) of 176dB while maintaining FoMs over 165dB in most configurations, and occupies only 0.1mm2 of silicon area.

This work proposes a dithered-digital-mixing background timing-skew calibration method for time-interleaved (TI) analog-to-digital converters (ADCs). Unlike prior digital-mixing methods that limit the input bandwidth or lead the calibration process to a limit cycle, the proposed method enhances the input bandwidth to the Nyquist frequency and guarantees the convergence. This is achieved by a pseudo-random binary sequence generator that produces a dither signal. Practical considerations including thermal noise and the step size of variable delay lines are discussed. Behavioral simulation results demonstrate the effectiveness of the proposed method with an improvement of signal-to-noise-and-distortion ratio from 26.3dB to 52.6dB for a 5GS/s 9b 16-channel TI ADC.

High-speed time-interleaved analog-to-digital converters (TI-ADCs) are sensitive to timing skew mismatch. Autocorrelation-based background timing skew calibration techniques require small hardware overhead as they rely on the TI-ADC input signal for calibration. However, such techniques suffer from a very long convergence time. This paper proposes a new correlation-based technique that boosts convergence speed by orders of magnitude compared to existing autocorrelation-based techniques. The technique uses a digital window detector and calculates the signal correlation funnction around zero-crossings only. Practical design considerations including thermal noise, clock jitter, quantization and offset mismatch are discussed. Behavioral simulation results for two TI-ADCs with different speeds, resolutions and interleaving factors are presented.

This paper presents a second-order VCO-based $\Delta\Sigma$ ADC with a fully digital feedback adder, which is highly digital, area efficient and low power. Both the first and second loop integrator are implemented by VCOs and are free of OTA. A novel digital adder is proposed to realize the secondary feedback, significantly reducing the power and area of the second stage. The proposed ADC is designed in a 28nm CMOS technology under 0.9V supply, consuming only 1.14mW. The simulated SNDR and SFDR are 72.5dB and 84.1dB respectively over a 5MHz signal bandwidth.