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Weiyuan Fang

dblp:376/2469 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0002-6149-297XORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Automated reasoning and model checking · 61% Logic in computer science · 39%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Automated reasoning and model checking › satisfiability
LTL satisfiability checking
0.812024
Learning to Check LTL Satisfiability and to Generate Traces via Differentiable Trace Checking · ISSTA 2024
Logic in computer science
temporal logic
0.812024
Learning to Check LTL Satisfiability and to Generate Traces via Differentiable Trace Checking · ISSTA 2024
Logic in computer science › temporal logic
linear temporal logic
0.212024
Learning to Check LTL Satisfiability and to Generate Traces via Differentiable Trace Checking · ISSTA 2024

Methods — techniques the papers use, named apart from their topics

neural network · 0.8gradient descent · 0.8differentiable trace checking · 0.8
YearPublicationVenuePosition
2024 Learning to Check LTL Satisfiability and to Generate Traces via Differentiable Trace Checking
abstract
Linear temporal logic (LTL) satisfiability checking has a high complexity, i.e., PSPACE-complete. Recently, neural networks have been shown to be promising in approximately checking LTL satisfiability in polynomial time. However, there is still a lack of neural network-based approach to the problem of checking LTL satisfiability and generating traces as evidence, simply called SAT-and-GET, where a satisfiable trace is generated as evidence if the given LTL formula is detected to be satisfiable. In this paper, we tackle SAT-and-GET via bridging LTL trace checking to neural network inference. Our key theoretical contribution is to show that a well-designed neural inference process, named after neural trace checking, is able to simulate LTL trace checking. We present a neural network-based approach VSCNet. Relying on the differentiable neural trace checking, VSCNet is able to learn both to check satisfiability and to generate traces via gradient descent. Experimental results confirm the effectiveness of VSCNet, showing that it significantly outperforms the state-of-the-art (SOTA) neural network-based approaches for trace generation, on average achieving up to 41.68% improvement in semantic accuracy. Besides, compared with the SOTA logic-based approach nuXmv and Aalta, VSCNet achieves averagely 186X and 3541X speedups on large-scale datasets, respectively.
Weilin Luo, Pingjia Liang, Junming Qiu, Polong Chen, Hai Wan, Jianfeng Du, Weiyuan Fang
ISSTA7