Long-term data remanence in SRAMs can pose serious security risks when ICs containing sensitive information are discarded at the end of their operational life. Sensitive information can fall into unauthorized hands if these ICs are not sanitized properly. Traditionally, data remanence has been addressed primarily in DRAM and flash memories, while SRAMs have been overlooked due to very short retention periods. Hovanes et al. [1] demonstrated that SRAMs are vulnerable to data remanence attacks, which can retrieve static data, such as firmware and keys. Their method exploits aging-induced imprints on power-up states, enabling partial recovery by comparing aged states with the originals. Although effective, this method requires maintaining records of all initial power-up states. In this paper, we propose a data recovery approach that does not require access to prior information. Our method also exploits data imprinting in SRAMs, but instead of using actual initial power-up states, we employ controlled aging to reconstruct them. Experiments on SRAM chips storing a binary image demonstrated near-complete recovery after 12 hours of controlled aging at 100◦C using 32 copies.

The modern semiconductor industry requires memory solutions that can keep pace with the high-speed demands of high-performance computing. Embedded non-volatile memories (eNVMs) address these requirements by offering faster access to stored data at an improved computational throughput and efficiency. Furthermore, these technologies offer numerous appealing features, including limited area-energy-runtime budget and data retention capabilities. Among these, the data retention feature of eNVMs has garnered particular interest within the semiconductor community. Although this property allows eNVMs to retain data even in the absence of a continuous power supply, it also introduces some vulnerabilities, prompting security concerns. These concerns have sparked increased interest in examining the broader security implications associated with eNVM technologies. This article examines the security aspects of eNVMs by discussing the reasons for vulnerabilities in specific memories from an architectural point of view. Additionally, this article extensively reviews eNVM-based security primitives, such as physically unclonable functions and true random number generators, as well as techniques like logic obfuscation. This article also explores a broad spectrum of security threats to eNVMs, including physical attacks such as side-channel attacks, fault injection, and probing, as well as logical threats like information leakage, denial-of-service, and thermal attacks. Finally, this article presents a study of publication trends in the eNVM domain since the early 2000s, reflecting the rising momentum and research activity in this field.

The surge in counterfeit Integrated Circuits (ICs) in the electronics supply chain, particularly those reclaimed from recycled components of old and discarded electronics, poses a significant threat to our critical infrastructures. Unfortunately, this threat persists due to the absence of effective detection techniques. In pursuing a reliable detection method, a previous study introduced the idea of identifying recycled ICs using SRAM power-up states, leveraging the inherent symmetry in the logic states of 0s and 1s in newly manufactured SRAM cells. However, in SRAMs produced with older technology nodes, the reference parameter of 50% 1s is often less prominent due to systematic design variation biasing all cells in a specific direction. To address this challenge, this paper proposes a robust self-referencing approach for detecting recycled ICs. The power-up states of an IC under test are segmented into subregions for similarity analysis of the percent of 1s within them. Our study establishes that the percent of 1s in all subregions of a newly manufactured IC is statistically more similar to each other than that in a recycled IC. Our experimental results demonstrate a substantial rise in the standard deviation of the percent of 1s for subregions in the aged SRAM, occurring after just a few days of aging. This approach aims to enhance the reliability of counterfeit IC detection, particularly in the context of older technology nodes where conventional methods may fall short.