Fully Homomorphic Encryption (FHE) allows one to outsource computation over encrypted data to untrusted servers without worrying about data breaching. Since FHE is known to be extremely computationally intensive, application-specific accelerators emerged as a powerful solution to narrow the performance gap. Nevertheless, due to the increasing complexities in FHE schemes per se and multi-scheme FHE algorithm designs in end-to-end privacy-preserving tasks, existing FHE accelerators often face the challenges of low hardware utilization rates and insufficient memory bandwidth. In this work, we present APACHE, a layered near-memory computing hierarchy tailored for multi-scheme FHE acceleration. By closely inspecting the data flow across different FHE schemes, we propose a layered near-memory computing architecture with fine-grained functional unit design to significantly enhance the utilization rates of both computational resources and memory bandwidth. In addition, we propose a multi-scheme operator compiler to efficiently schedule high-level FHE computations across lower-level functional units. In the experiment, we evaluated APACHE in various FHE applications, such as Lola MNIST, HELR, fully packed bootstrapping, and fully homomorphic processors. The results illustrate that APACHE outperforms state-of-the-art ASIC FHE accelerators by 10.63× to 35.47× over a variety of operator and application benchmarks.

Polynomial multiplication (PM) is the computational bottleneck of lattice-based cryptography, such as post-quantum cryptography (PQC). Designing dedicated hardware accelerators for polynomial multiplication is an effective solution to improve the execution speed. However, current mainstream designs ignore the impact of computing array size, resulting in poor design flexibility and low memory utilization. To address these issues, we propose Meta, a memory-efficient tri-stage PM accelerator. Our proposed tri-stage PM algorithm fuses all isolated substages into a unique stage named fused coefficient-wise multiplication (FCWM), ensuring efficient computation. Meanwhile, in different stages of the algorithm, the circuit of two-dimensional reconfigurable coupled butterfly units (2D-RCBFUs) is fine-grained reconfigured to improve resource utilization. Moreover, the low-complexity memory mapping scheme simplifies the address control logic and reduces the hardware overhead. Meta can efficiently support the PM of an arbitrary power of two, which is impossible for previous designs using a 2D computing array. Compared with the state-of-the-art designs, our Meta demonstrates the best memory utilization, achieving up to$10.0\times $performance improvement.