This paper presents a fully integrated NMOS stimulator using a hybrid dynamic bulk biasing technique (HDBT) and a charge-pump-like control technique (CCT) in a 180-nm bulk CMOS technology. HDBT integrates terminal-voltage-dependent and logic dynamic bulk biasing to set the bulk bias voltage according to the electrode voltage. CCT adds a DC voltage to the gate terminal through a diode and capacitor to help turn on the NMOS transistor. It helps turn off the transistor by shorting the source and gate terminals together and applying two diodes across the drain and source terminals. To achieve an electrode voltage higher than the breakdown voltage of substrate diode ($V_{\mathrm {BD}}$) with an independent power supply, a high voltage tolerant switch is proposed with HDBT and CCT. A high voltage interface is also proposed, utilizing the capacitor adaptive biasing, to overcome the limitation of$V_{\mathrm {BD}}$between the high and low voltage domains and to accommodate the variation of electrode voltage. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves a maximum electrode voltage ($V_{\mathrm {E,MAX}}$) of 18.74V under a 3.3-V supply, with a highest$V_{\mathrm {E,MAX}}$/$V_{\mathrm {BD}}$ratio of 1.27 than state-of-the-art stimulators, including non-standard technology designs. In a continuous output test mode over 10million cycles, the variation of$V_{\mathrm {E,MAX}}$is less than 150mV. The measured maximum residual voltage on the capacitor is 13.55mV.

This paper presents a hybrid all-NMOS rectifier with two gate-biasing techniques to extend the power dynamic range (PDR) for wireless power transfer. The proposed hybrid rectifier combines the strengths of the cross-connected (CC) and diode-based (DB) configurations, achieving both a high forward current and a small reverse current along the PDR. Additionally, two separate gate-biasing techniques are employed to optimize the gate bias voltage for the gate-biased-CC and gate-biased-DB parts, respectively. All transistors in the rectifier are NMOS transistors, which can minimize the total area when extended to multi-stage configurations. The circuit is implemented in a 180-nm CMOS process, occupying an area of 0.195 mm2. Experimental results show a sensitivity of -10.3 dBm with a 1 MΩ load and a peak power conversion efficiency of 78.6% at -7.4 dBm with a 3 kΩ load. In addition, the proposed rectifier achieves a PDR greater than 22.3 dB with loads below 5 kΩ.

This paper presents a self-powered parallel synchronized switch harvesting on inductor (P-SSHI) active rectifier with an energy-efficient adaptive switch control circuit. The energy-efficient adaptive switch control circuit reuses comparators within the active rectifier for both zero-crossing detection and voltage flipping detection, simplifying the switch control module. The proposed active rectifier incorporates an active diode and a MOSFET within each energy transfer path to mitigate the forward voltage drop across rectifying elements. The proposed P-SSHI circuit which includes a diode in each voltage flipping path shows high adaptability to different inductances. All the auxiliary circuits are powered by the storage capacitor. The proposed circuit is designed in 180 nm CMOS process, and the total occupied chip area is 0.18 mm2. The power dissipation of the switch control module is only 0.15 μW, owing to its simplicity. The simulation results show that the proposed design achieves a high voltage flipping efficiency of 85.4%. The maximum output power is 5.5 times greater than that of the ideal full-bridge rectifier.

This paper presents a fully integrated stimulator using a dynamic bulk biasing technique and a dynamic control scheme in a 180-nm bulk CMOS technology. Unlike the conventional bulk biasing method, the bulk bias voltage is dynamically set according to the different stimulation phases. It avoids the underlying leakage current paths, and improves the maximum stimulation voltage compliance (MSVC). Together with dynamic bulk biasing scheme, a high voltage interface is designed to overcome the limitation of the breakdown voltage of the substrate diode ( V$_{\mathbf{BD}}$) between the high and low voltage domains. An all-NMOS dynamic charge pump is also proposed as a dynamic power supply above V$_{\mathbf{BD}}$and provides dynamic bulk-biasing voltages. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves an MSVC of$\pm$16.5 V under a 3.3-V supply, and the achieved MSVC is$\sim$1.11 times higher than the V$_{\mathbf{BD}}$($\sim$14.8 V) of the substrate diode. The stimulator is also measured in a continuous output test mode for over 10 million cycles, the variation of$\vert$MSVC$\vert$is less than 200 mV.