The goal of design and technology co-optimization (DTCO) is to find a combination of parameter options (i.e., parameter setting values) of target process technology that enables to produce a target design implementation of optimal PPA (performance, power, area). Since the number of parameters sharply increases as the technology scales, recently, lots of attention has been paid to automating this DTCO process in both semiconductor foundry and academic research community. This paper addresses the problem of a full DTCO automation that deals with analyzing the numerous parameter options at advanced technology nodes. Precisely, we develop a machine learning (ML) based DTCO automation framework, which supports three key features: (1) an effective analysis on the changes of DTCO parameter options within an acceptable runtime; (2) a full exploration of chip/block-level PPA metrics through automatic standard cell (SC) library generation, for which we develop a new technique that enables to accelerate the iterative physical design process; (3) supporting both of Complementary FET (CFET) based SCs and multi-row-height SCs to account for future generation technology. Through experiments with benchmark circuits, it is shown that our DTCO automation framework is able to accurately predict the direction and magnitude of PPA changes of target designs with 5x sampling efficiency. In addition, it is shown that our SC layout generator supporting CFET and multi-rowheight SCs provides a timely DTCO process relevant to ongoing technology advancements.

This paper presents a new approach to the problem of improving pin accessibility, which has become an important task for physical design at the advanced technology nodes. To this end, we propose a new concept, called disclosed-pins, which allows to daringly expose some pins of standard cells across the cell boundary, which otherwise, there would be no way to boost pin accessibility. However, it requires two key issues that should be resolved to make the disclosed-pin concept fully effective. Those are (1) how can we systematically synthesize diverse structures of standard cells with disclosed-pins? and (2) how can we effectively exploit those cells in the course of chip implementation? Precisely, for issue 1, we propose a new in-cell routing method combined with disclosed-pin generation, developing it based on an SMT (satisfiability modular theory) formulation, while for issue 2, we develop a post-place optimization, in which we optimally replace, on a row-basis, the cell instances with low pin accessibility in a row by the cells with disclosed-pins, formulating it into an instance of DP (dynamic programming). In the meantime, through experiments with benchmark circuits, it is shown that our proposed methodology utilizing our synthesized cells with disclosed-pins can considerably relieve the burden in block-level routing, resulting in reducing the number of design rule violations by 26.05% and 22.80% on average over that produced by the state-of-the-art prior methods of pin pattern (internal) extension and dummy poly insertion, respectively.

In this paper, a new approach to the problem of synthesizing standard cells is presented. The top priority objective in the conventional approaches has been invariably placed on minimizing cell area. However, in our approach, we place the top priority on minimizing cell delay as opposed to minimizing cell area, which has never been addressed as yet, but is very valuable and highly important for implementing high-performance chips at advanced technology nodes. Precisely, we propose a totally different approach, developing a cell delay driven layout synthesis method, which is composed of three steps: (1) a critical path driven transistor placement, which is formulated into a search tree based exhaustive placement enumeration, employing an effective pruning technique, followed by (2) an optimal transistor folding, formulating it into an instance of DP (dynamic programming) to reduce cell area by maximizing the occurrences of diffusion sharing and minimizing the oxide diffusion jog rule violations, then (3) an optimal critical net driven in-cell routing, formulating it into an instance of SMT (satisfiability modulo theory) problem. In the meantime, through experiments with benchmarks, it is shown that our cell synthesis approach is able to produce cells with up to 9.3% shorter delay. More importantly, by using those cells, we are able to increase the circuit clock frequency by 7.2% on average while retaining nearly the same chip area and power consumption over that produced by using the conventional cells.

To generate standard cell (SC) layouts of competitive quality, pin accessibility and in-cell routing congestion should be thoroughly taken into account. In this work, we develop a new tool to address this issue. Precisely, we (1) develop a technology compilation module that can convert diverse cell architectures and design rules into grid based design parameters and layer configuration, (2) generate optimal FET placement using metrics that can accurately and efficiently predict intra-cell pin accessibility and in-cell routing congestion, and (3) introduce the concept of ghost-via and ghost-metal, and formulate in-cell routing using satisfiability modulo theory for pin separation and extension. Experimental results show that our system is able to synthesize SC layouts with a routing completion rate of 95~98 %, which is far better than the previous SC layout generator, and produce layouts comparable to the ARM's hand-crafted layouts. In addition, the design implementations produced by using our 2-layer ID SC library exhibit on average 76.6% fewer design rule violations (DRVs) with similar or better quality of timing and area, while in comparison with that produced by using the library of hand-crafted ARM SCs, the implementations produced by using our L-layer 2D SC library exhibit on average 11.7% smaller area with comparable timing and DRV count.

In this paper, we address three core problems in the layout synthesis of multi-row standard cells: transistor folding, row partitioning, and transistor placement. We propose a comprehensive solution to the problem of synthesizing area-optimal multi-row standard cells by seamlessly integrating transistor folding and row partitioning into the transistor placement framework. Additionally, we introduce a systematic methodology to construct a standard cell library. This methodology determines the cell types among single-row, multi-row with VDD-abut, and multi-row with VSS-abut in order to achieve an optimal trade-off between power, performance, and area (PPA) for the target design implementation. Experimental results demonstrate that for 4-routing track standard cells of the advanced technology nodes our multi-row cell generator increases the cell generation completion ratio from 72% to 100% and reduces the metal length for in-cell routing by 11.9% while maintaining comparable cell area compared to the area-minimal single-row cells. Furthermore, using our optimized cell library is able to reduce the target chip area by 4.2% and chip power by 7.0%, while all meeting timing and design rule constraints, compared to the state-of-the-art single-row standard cell library.