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Ihsane Tahir

dblp:378/6947 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0007-7773-1716ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 91% Hardware accelerators and domain-specific architectures · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › computer arithmetic
floating-point arithmetic
0.812024
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation · IEEE Trans. Computers 2024
Processor architecture and microarchitecture
instruction set architecture
0.812024
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation · IEEE Trans. Computers 2024
Processor architecture and microarchitecture › instruction set architecture › ISA extension
RISC-V ISA extension
0.812024
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation · IEEE Trans. Computers 2024
Hardware accelerators and domain-specific architectures
scientific computing accelerator
0.212024
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation · IEEE Trans. Computers 2024

Methods — techniques the papers use, named apart from their topics

rounding mode support · 0.8hardware-assisted prefetching · 0.8
YearPublicationVenuePosition
2024 Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation
abstract
A key concern in the field of scientific computation is the convergence of numerical solvers when applied to large problems. The numerical workarounds used to improve convergence are often problem specific, time consuming and require skilled numerical analysts. An alternative is to simply increase the working precision of the computation, but this is difficult due to the lack of efficient hardware support for extended precision. We proposeXvpfloat, a RISC-V ISA extension for dynamically variable and extended precision computation, a hardware implementation and a full software stack. Our architecture provides a comprehensive implementation of this ISA, with up to 512 bits of significand, including full support for common rounding modes and heterogeneous precision arithmetic operations. The memory subsystem handles IEEE 754 extendable formats, and features specialized indexed loads and stores with hardware-assisted prefetching. This processor can either operate standalone or as an accelerator for a general purpose host. We demonstrate that the number of solver iterations can be reduced up to 5× and, for certain, difficult problems, convergence is only possible with very high precision (≥384 bits). This accelerator provides a new approach to accelerate large scale scientific computing.
Eric Guthmuller, César Fuguet Tortolero, Andrea Bocco, Jérôme Fereyre, Riccardo Alidori, Ihsane Tahir, Yves Durand
IEEE Trans. Computers6