The rising size and complexity of in-car networks call for more advanced and scalable verification solutions. We propose a verification methodology for in-car networks based on a system level test generator tool used for creating massive random biased stimuli, and on coverage and checking monitors. The test generator is an expert system based on an ontology of testing knowledge. A significant challenge is the continuous nature of the stimuli needed to represent the physical environment and the state of the internal components controlled by the vehicle's electronic systems. We report on applying our methodology to an example in-car network simulator.

In a modern chip development cycle non-mainline / nonfunctional verification is gaining importance compared to traditional functional verification tasks and takes up to one third of the total verification effort. The purpose of non-mainline logic is to operate, maintain, and debug the chip. Ever-increasing complexity of the chip, thus, directly affects the complexity of the non-mainline logic and as a result, the verification thereof. Moreover, the non-mainline world is no longer pure hardware, but an intricate mix of software and hardware.

With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.

Verifying new hardware systems is a daunting task. To reduce the amount of effort involved, verification teams attempt to reuse as much verification IP as possible. We introduce a novel approach for test generation that enables the reuse of verification IP to verify new functionality. This method applies to a significant category of features, which are variations on the functionality of an existing design. Our method is being successfully used in the verification of high-end IBM servers: System p and System z. We compared our technique to alternative approaches and show that it achieves the best quality while reducing manual effort.