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This work presents a lightweight, fully digital, unsupervised calibration method for SAR ADCs that directly targets harmonic distortion without relying on costly FFT or supervised training techniques. Distortion is estimated from a small, configurable set of harmonic bins using a time-multiplexed fixed-point Goertzel engine, such that the objective-function cost scales linearly with the number of tracked harmonic spurs, remains independent of the acquisition length, and decouples calibration memory from the number of acquired samples. A particle swarm optimizer then updates a decoder that re-maps raw SAR codes to calibrated reconstruction levels under bounded constraints. Guided by a distortion-based quantizer view that clarifies the role of non-invasive code re-interpretation, the proposed method removes converter distortion with negligible overhead, requiring only a 56 B LUT decoder and an adder tree. Measurements on 50 MS/s differential SAR ADC in 22 nm FD-SOI across five chip instances show that, with K=28 tracked harmonics, |THD| improves from 68.15 dB up to 78.04 dB (+9.89 dB), demonstrating best-in-class harmonic spur suppression up to the quantization noise limit, outperforming the SotA across PVT variations and input frequencies, while maintaining sub-mW power consumption.

This article presents adiabatic data transmitters using stepwise driving to improve the energy efficiency of low data-rate sensor nodes beyond theCV2limitation. Stepwise driving is applied to NRZ and PAM-4 modulations, supporting data rates of hundreds of Mb/s, required by micro-controller peripheral I/O interfaces in sensor nodes. Fabricated in 22nm CMOS, the proposed transmitter drivers achieve over 64% energy savings at 200 Mb/s compared to conventionalCV2drivers.

This paper presents the design of a 4-bit Single Slope (SS) ADC adopting reset counting method for current mode in-memory computing (IMC) acceleration in 28nm SLPe technology. Two types of comparators are combined for enhanced power efficiency and lower kickback noise, achieving 50.2 fJ/conv Walden FoM at a reduced area footprint of 101.6 µm2. Finally, the SS-ADC is integrated with a 1FeFET1R macro to compute multiply-accumulate (MAC) operations for convolutional or fully connected layers in neural networks. Furthermore, the SS-ADC offers the possibility for higher resolution and the integration of analog non-linear activation function, reducing the digital overhead in neural network accelerators.

This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nVrmsin a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%.

In this paper, we analyze faradaic DC current (FC) generated by inherent offset charge (IOC) and charge mismatch. Under frequent shorting, the analysis shows that mismatch- induced DC current is small compared to IOC-induced DC current. To reduce the FC, we propose a biphasic pulse scheme which compensates the IOC. Simulation results show the proposed pulse scheme reduces the FC by about 58 times compared to a conventional biphasic pulse.

The papers in this special section focus on smart edge computing and the Internet of Things (IoT). The evolution of the (IoT) is changing the nature of edge-computing devices. Availability of novel sensor interfaces, efficient digital low power processors, and high-bandwidth low-power communication protocols have generated a perfect storm within the IoT ecosystem. Next generation IoT end-nodes have to support, in place, an increasing range of functionality: multi-sensory data processing and analysis, complex systems control strategies, and, ultimately, artificial intelligence. These new capabilities will enable disruptive innovation in wearable and implantable biomedical devices, autonomous insect-sized drones, miniaturized devices for environmental sensing and continuous monitoring of buildings, industrial machinery, power grids. As a result, we witness a paradigm shift towards computationally demanding tasks on tiny form-factor devices at extreme energy efficiency.

A first-order time-based ΔΣ modulator using voltage-controlled oscillator (VCO) is presented. The proposed modulator employs phase interpolation technique to enhance the time resolution of the VCO and digital calibration to improve the linearity of the VCO tuning curve. The proposed modulator, implemented in 0.13 μm CMOS process, achieves 55 dB peak signal-to-noise ratio and 52.5 dB peak signal-to-noise-and-distortion ratio at 600 MHz sampling frequency for 20 MHz input bandwidth and consumes 14.3 mW.