Demo Data from EDBT 2026 / reviewers in the wild / expert
Tatsuo Nomura
dblp:38/10441
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
High-performance computing · 50% GPUs and heterogeneous computing · 50% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing › GPU computing › GPGPU acceleration
GPU-accelerated supercomputing |
0.1 | 1 | 2011 | Physis: an implicitly parallel programming model for stencil computations on large-scale GPU-accelerated supercomputers · SC 2011 |
High-performance computing
stencil computation |
0.1 | 1 | 2011 | Physis: an implicitly parallel programming model for stencil computations on large-scale GPU-accelerated supercomputers · SC 2011 |
Compilers and program optimization
code generation |
0.0 | 1 | 2011 | Physis: an implicitly parallel programming model for stencil computations on large-scale GPU-accelerated supercomputers · SC 2011 |
Methods — techniques the papers use, named apart from their topics
implicit parallelism · 0.2computation-communication overlap · 0.2MPI · 0.2CUDA · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | Physis: an implicitly parallel programming model for stencil computations on large-scale GPU-accelerated supercomputersabstractThis paper proposes a compiler-based programming framework that automatically translates user-written structured grid code into scalable parallel implementation code for GPU-equipped clusters. To enable such automatic translations, we design a small set of declarative constructs that allow the user to express stencil computations in a portable and implicitly parallel manner. Our framework translates the user-written code into actual implementation code in CUDA for GPU acceleration and MPI for node-level parallelization with automatic optimizations such as computation and communication overlapping. We demonstrate the feasibility of such automatic translations by implementing several structured grid applications in our framework. Experimental results on the TSUBAME2.0 GPU-based supercomputer show that the performance is comparable as hand-written code and good strong and weak scalability up to 256 GPUs. Naoya Maruyama, Tatsuo Nomura, Kento Sato, Satoshi Matsuoka |
SC | 2 |