Logs are a known abstraction used to develop dependable and secure distributed systems. By logging entries on a sequential global log, systems can synchronize updates over replicas and provide a consistent state recovery in the presence of faults. However, their usage incurs a non-negligible overhead on the application's performance. This article presents Beelog, an approach to reduce logging impact and accelerate recovery on log-based protocols by safely discarding entries from logs. The technique involves executing a log compaction during run-time concurrently with the persistence and execution of commands. Besides compacting logging information, the proposed technique splits the log file and incorporates strategies to reduce logging overhead, such as batching and parallel I/O. We evaluate the proposed approach by implementing it as a new feature of the etcd key-value store and comparing it against etcd's standard logging. Utilizing workloads from the YCSB benchmark and experimenting with different configurations for batch size and number of storage devices, our results indicate that Beelog can reduce application recovery time, especially in write-intensive workloads with a small number of keys and a probability favoring the most recent keys to be updated. In such scenarios, we observed up to a 50% compaction in the log file size and a 65% improvement in recovery time compared to etcd's standard recovery protocol. As a side effect, batching results in higher command execution latency, ranging from$ \text{100 ms}$to$ \text{350 ms}$with Beelog, compared to the default etcd's$ \text{90 ms}$. Except for the latency increase, the proposed technique does not impose other significant performance costs, making it a practical solution for systems where fast recovery and reduced storage are priorities.

Single Event Transient (SET) faults are more notable every day at Earth applications. Even considering FinFET technology, the effects are not negligible. A circuit-level evaluation of radiation effects must consider each internal node of the cells, input vectors, particle type, and pulse width derived from the particle collision to determine the sensibility of the circuit under evaluation. Moreover, circuit characterization is time-consuming, involving many electrical simulations to reach an appropriate precision, mainly considering together with the process variability effects. This work evaluates how process variability and gate mapping impacts the radiation robustness on circuits composed by multigate devices in 7 nm FinFET technology. Firstly, the NAND2 and NOR2 gates are evaluated at nominal conditions and considering the process variability impact on the radiation sensitivity. After that, three different topologies of the same circuit are analyzed, showing that even when considering process variability, the circuit's robustness is highly dependent on its output gates and that the most sensitive part of a circuit may vary given process variability. Results also show that the$\mathbf{LET}_{th}$value may vary by order of magnitude due to the work-function fluctuation of NMOS and PMOS devices.

Technology advancements have enabled us to manufacture integrated circuits composed of a sheer number of gates onto a single chip. However, these enhancements have also introduced new challenges. In physical synthesis, the placement and routing steps have to satisfy even more complex design rules while optimizing the solution quality. However, the search for wirelength optimization may lead the placement engine to produce an infeasible routing solution, making it necessary to repeat previous steps and increase the overall project cost. Traditionally, placement algorithms estimate routability using pin density because of its low computational cost. Nonetheless, in advanced technology nodes, this has become inefficient due to more restrictive manufacturing constraints and complex standard cell layouts. Although many placement techniques propose to address routability, the problem is that these models rely on specific heuristics or designer experience. Therefore, we propose a machine learning-based framework for addressing routability during the placement step.

In recent years, Approximate Computing has been gaining space as a technique for tackling energy requirements in error-resilient applications, while the usage of Machine Learning systems has steadily increased. This work explores two different approaches for approximation in comparator circuits and their impact on Decision Tree applications, observing power and accuracy metrics. Two gate-level architectures are proposed for dedicated comparators, approximating 25% or 50% of least significant bits using different techniques. The circuits were described in 7 nm FinFET technology. The approximate comparators were then evaluated in a Decision Tree classification model using five continuous and mixed attribute datasets. The 25% LSB approximate comparator proposed improves the energy efficiency in Decision Tree applications, reducing from 12% up to 84% the power per inference while presenting minor deviations in accuracy compared to the exact baseline.

The increasing use of Machine Learning applications has caused a high demand for design techniques targeting the trade-off between energy consumption and accuracy in inference models. In this scenario, Decision Trees are models widely used in embedded systems and Internet of Things applications. They are less resource intensive than Neural Networks, and maintain acceptable accuracy results for various problems. This project proposes a framework for evaluating the improvement of the power-accuracy trade-off in decision tree models using approximate circuits. The results of the electrical evaluation and accuracy provided in each step are obtained by applying different approximation and quantization techniques. This information can be used together with power-accuracy metrics to find the best comparator circuits for different applications of Decision Trees and dedicated hardware requirements.

The demand for power-efficient circuits is increasing everyday due to the large demand for portable devices and Internet of Things applications. Filters, Digital Signal Processing, Machine Learning applications involves large amount of data handling, demanding for hardware designers fast and low-power arithmetic circuits, mainly multipliers. The main goal of this work is to evaluate multiplier circuits in order to explore approximate computing approaches for power-efficient scenarios, mainly considering machine learning and Internet of Things applications. At the end, the set of information provided will support designers to choose the best approximate multiplier according to the design requirements.

Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning.

This work evaluates the use of Decision Trees (DTs) methods for a fast logic minimization of Boolean functions. The proposed DT approach is compared to traditional Espresso logic minimizer and the minimization algorithms available in the ABC tool. The methods are compared with respect to the execution time, number of nodes and number of logic levels. The DT methods proved to be a faster alternative, reducing time by an average of 52% and 5.5% when compared to Espresso and ABC respectively, while keeping competitive results in terms of AIG depth and number of nodes. Additionally, in order to obtain smaller circuits at the cost of approximate results we tested DTs with limited tree depth. The trade-offs between synthesis time, circuit area and accuracy are also discussed. Compared to ABC, limiting the maximum tree depth leads to time savings of up to 52%, up to 86% less number of nodes, and up to 48% lower AIG depth, while maintaining acceptable accuracy results.

The Gaussian image filter is a compute-intensive approach to reduce undesirable artifacts and generally serves as a pre-processing technique for emerging applications related to visual computing systems. This work evaluates alternatives for the design of power-efficient Gaussian Filters. The proposed optimization strategy combines: 1) a refactored function to minimize the arithmetic operations, and 2) a design space exploration investigating different approximation scenarios applied to the full adders. The exact version of our refactored Gaussian Filter architecture reduces the total power consumption and the circuit area by 18% and 12%, respectively compared with the baseline Gaussian Filter architecture. Moreover, the combination of different approximation levels with the refactored architecture provides design options with power reductions from 21% to 59% compared with the baseline Gaussian Filter architecture.

Advanced technologies introduce new challenges as higher process variability impact and tight power constraints, mainly for IoT applications. Schmitt Trigger inverters are traditionally used for noise immunity enhancement due to their hysteresis characteristic, and have been recently applied to mitigate radiation effects and process variability impact. Alongside, Stacked-Inverter Gates are applied for gain increase, consequently, robustness enhancement as well. Thus, the main contribution of this paper is to investigate the relationship between transistor sizing, supply voltage, energy, and process variability robustness to get a minimal energy consumption circuit with FinFET technology, while keeping robustness and to identify the recommended circuit for different applications. Results show that adjusting the supply voltage and transistor sizing, at a high variability scenario, it is possible to decrease the energy consumption up to 32.19% while maintaining adequate robustness. It was possible to show a considerable difference concerning the Schmitt Trigger noise-immunity characteristics, in comparison to other designs, over supply voltage and variability scaling.

Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability, which can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both nominal conditions and considering the impact of process variability. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.

The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability. Traditionally, complex gates are adopted to reduce area, delay and power consumption. However, they can introduce challenges related to a robustness that might be avoided with more regular and basic cells. This extended abstract presents my current research works. Firstly, the different works performed in my research are described. Then, a short version methodology and the main results are presented.

The emergence of IoT alongside with the increased process variability impact in modern technology nodes, is the main reason to control variability impact over metrics. Given the large set of IoT devices working in battery-oriented environments, energy consumption should be minimal and the operation regime reliable. Schmitt Trigger inverters are traditionally used for noise immunity enhancement, and have been recently applied to mitigate radiation effects and process variability impact. However, Schmitt Trigger operation at the nominal voltage introduces high degradation on power consumption. Thus, the main contribution of this paper is to identify the relationship between transistor sizing, supply voltage, energy, and process variability robustness to get a minimal energy consumption circuit while keeping robustness. The results are extracted from 7-nm FinFET Schmitt Trigger layouts under different levels of process variability, supply voltages, and sizing. Also, a maximum frequency scaling under a failure threshold was performed. On average, the supply voltage decreases in layouts with a smaller number of fins, while maintaining acceptable robustness in high variability scenarios. Exploring voltage and transistor sizing made possible a reduction of about 24.84% of power consumption.

With battery-oriented applications rising in IoT, alongside the challenge of supplying electrical power, a reliable energy consumption metric must be satisfied. Although, variability has emerged as one of the critical threats to reliable metrics making the development of robustness techniques necessary. Schmitt Trigger Inverters haye been applied in designs due to its hysteresis characteristic, improving robustness. Still, Schmitt Triggers at nominal values of supply voltage may cause high degradation on power consumption. Thus, this work aims to indicate the appropriate dimensioning and supply voltage value for minimum energy consumption whOe preserving adequate robustness. It was found that the appropriate dimensioning and supply voltage can reduce up to 26.31% energy consumption.

The yield optimization and radiation hardness are relevant reliability requirements as chip manufacturing advances more in-depth into the nanometer regime. One way to obtain improvements in these issues is by applying techniques to mitigate the effects of process variability and radiation-induced soft errors in the circuits. This work reports the use of three circuit-level approaches in FinFET designs as well as point out the pros and cons of adopting it.

This paper evaluates the benefits and drawbacks of using Schmitt Trigger (ST) inverters to minimize process, voltage and temperature variability effects on full adders. Variability mainly affects the energy outcomes on full adders, and the use of ST techniques can decrease up to 80% the energy deviation. However, it implies in a significant increase on the energy consumption. Considering the pros and cons, Mirror CMOS FA is the most beneficiated with the ST inverters, with a small impact on the average delay and a significant reduction in the energy and delay deviation.

The high integration capacity of digital circuits, which occurs due to technological scaling, presents new challenges for nanotechnology designs. The evolution of integrated circuits has made them more susceptible to faults, besides increasing the process variability, which can lead to circuits operating outside their specification ranges. This work evaluates the effects of process variability and radiation faults on complex gates. These effects are compared to alternative circuits that implement the same functions but exploring a multi-level of basic cells as NAND2, NOR2 and Inverters. The technology adopted is 7nm FinFET ASAP. Results show that although complex cells present better timing and power results, multi-level circuits are up to 28% less sensible to radiation faults and about 40% more stable under process variability.

This work provides a detailed set of predictive data about FinFET and Trigate devices behavior considering process variability effects in ON and OFF currents. These evaluations help to understand the impact of variability sources identifying relevant behavior standards with respect to the use of FinFET and Trigate devices. The IOFFsuffers the higher impact of geometric variability, mainly on FinFET devices. PFET devices and the LSTP model are also more sensitive than NFET devices and high performance models. Results highlights that Trigate devices are up to 10% less sensitive to gate length variations.

This paper investigates the impact of the main sources of variation on performance and power consumption for different transistor sizing techniques applied to cells in FinFET technologies. The analysis considers process, voltage and temperature variations, individually. Voltage and temperature variations are combined to obtain an insight into their contributions. Results are useful to define the variability contributions in the early design steps and to select the most appropriate transistor sizing technique for a targeted application. Results provide a quantitative understanding of each contribution considering a 14nm FinFET technology.

The availability of multimillion Commercial-Off-The-Shelf (COTS) Field Programmable Gate Arrays (FPGAs) is making now possible the implementation on a single device of complex systems embedding processor cores as well as huge memories and ad-hoc hardware accelerators exploiting the programmable logic (Systems on Programmable Chip, or SoPCs). When deployed in safety- or mission-critical applications, as avionic- and space-oriented ones, Singe Event Effects (SEEs) affecting COTS FPGA, which may have catastrophic effects if neglected, have to be considered and SEE mitigation techniques have to be employed. In this paper we explore the adoption of known techniques (such as lockstep, checkpointing and rollback recovery) for SEE mitigation to processors cores embedded in SoPCs, and propose their customization, specifically addressing the characteristics of programmable devices. Since the resulting design flow can easily be supported by automation tools, its adoption is particularly suitable to reduce the design and validation costs. Experimental results show the effectiveness of the proposed approach when compared to conventional TMR-based solutions.