Recently, processors have begun integrating 3D stacked DRAMs with the cores on the same package, and there have been several approaches to effectively utilizing the on-package DRAMs as caches. This article presents an approach that combines the previous approaches in a synergistic way by devising a module called the dirty-block tracker to maintain the dirtiness of each block in a dirty region. The approach avoids unnecessary tag checking for a write operation if the corresponding block in the cache is not dirty. Our simulation results show that the proposed technique achieves a 10.3% performance improvement on average over the state-of-the-art DRAM cache technique.

Using independent voltage (and frequency) domains for cores and caches allows us to achieve high energy efficiency since it enables operating the cores and caches at their own optimal voltages. However, it incurs a clock synchronization problem between the core and cache voltage domains. One of the conventional solutions is to add asynchronous FIFOs on the domain crossing boundary, but it degrades performance due to the increased latency. This paper presents a dynamic clock synchronization scheme between two different voltage domains. It uses a fast clock phase detector to monitor the clock phase difference between two voltage domains, a variable delay element consisting of multiple-stage thyristor-like delay circuits to support a wide delay range, and a small hardware module that uses the phase detector output to control the variable delay element. In this way, the scheme automatically adjusts the delay of a clock until the phase is aligned with that of the other clock. Also presented is an algorithm that speeds up the synchronization process. Experimental results show 1.4× speedup and 13% energy saving on average compared to the conventional approach.

In this paper, we present reconfigurable multiprocessor architecture for volume rendering. The multiprocessor consists of sixteen reconfigurable processors to exploit data parallelism of the volume rendering. Each processor has VLIW core and reconfigurable coarse-grained array specialized for control and data-intensive part of the program, respectively. The coarse-grained array can be configured dynamically, so that it can efficiently process different kernels of the volume rendering. The multiprocessor is implemented using verilog HDL and realized onto a commercial FPGA-based prototyping system. The experimental result shows that the presented multiprocessor has comparable performance to high-end desktop GPUs.

In frame memory recompression, decompression latency consists of two components, i.e., memory access cycles for compressed data fetch, and decompression time. Compared to most earlier works which mainly focused on the compression ratio and, therefore, only reducing memory access cycles, this paper proposes a low-latency variable-length coding method called non-zero bit selection scheme (NBS). The proposed NBS enables highly parallel decompression achieving a three-cycle decompression for an 8×8 block, compared to previous methods requiring as many as twelve clock cycles for the case of exponential Golomb code. It is notable that the proposed NBS scheme has achieved this without deterioration of the compression ratio. Experimental result on a number of full HD videos shows that the compression ratio of the proposed method is at least not worse than that obtained with the exponential Golomb code on the average, while reducing the decompression time to 25% compared to the exponential Golomb code.

A widely-used block matching algorithm (BMA) for error concealment may suffer from the deteriorated quality of a concealed block that includes multiple objects in different motion directions. This paper proposes an edge-adaptive BMA that decomposes a damaged 16 times 16 macroblock (MB) into four 8 times 8 blocks and conceals the 8 times 8 blocks together only when they belong to the same object. The edge-adaptive BMA detects edges on MB boundaries and uses the number and positions of the edges to determine which 8 times 8 blocks belong to the same object. The proposed algorithm improves PSNR by an average of 0.27 dB compared with the existing BMA for error concealment.

The paper presents a scheme for efficient channel usage between simulator and accelerator, where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-simulation while the simulator runs a transaction-level model of the remaining part of the whole chip being verified. With conventional simulation, accelerator evaluations of simulator and accelerator alternate at every valid simulation time, which results in poor simulation performance due to the startup overhead of simulator-accelerator channel access. The startup overhead can be reduced by merging multiple transactions on the channel into a single burst traffic. We propose a predictive packetizing scheme for reducing channel traffic by merging as many transactions into a burst traffic as possible based on 'prediction and rollback'. Under ideal conditions with 100% prediction accuracy, the proposed method shows a performance gain of 1500% compared to the conventional one.