This paper presents a solution to the problem of performance-driven buffered routing tree generation for very large scale integrated circuits. Using a novel bottom-up construction algorithm and a local neighborhood search strategy, our polynomial time algorithm finds the optimum solution in an exponential-size solution subspace. The final output is a buffered rectilinear Steiner routing tree that connects the driver of a net to its sink nodes. The two variants of the problem, i.e. maximizing the required time at the driver subject to a maximum total area constraint and minimizing the total area subject to a minimum required time at the driver constraint, are handled by propagating three-dimensional solution curves during the construction phase. Experimental results demonstrate the effectiveness of our algorithm compared to other techniques.

This paper presents a solution to the problem of performance-driven buffered routing tree generation in electronic circuits.Using a novel bottom-up construction algorithm and a local neighborhood search strategy, this method finds the best solution of the problem in an exponential size solution subspace in polynomial time.The output is a hierarchical buffered rectilinear Steiner routing tree that connects the driver of a net to its sink nodes.The two variants of the problem, i.e. maximizing the driver required time subject to a total buffer area constraint and minimizing the total buffer area subject to a minimum driver required time constraint, are handled by propagating three-dimensional solution curves during the construction phase.Experimental results prove the effectiveness of this technique compared to the other solutions for this problem.

This paper presents a set of techniques and a new design flow to be used in the synthesis of high-performance deep-submicron logic circuits. The design flow consists of circuit partitioning into tree like clusters, floorplanning, global routing, and timing analysis/budgeting steps, followed by simultaneous technology mapping and linear placement of each cluster. The strength of this approach lies in the dynamic programming-based algorithms used in performing simultaneous technology mapping and linear placement of the logic clusters. The two algorithms we propose, one for exact total (gate plus routing) area minimization and the other for total (gate plus routing) delay minimization, generate a set of noninferior solutions for each cluster enabling designers to perform tradeoffs between total-area and total-delay. Experimental results on large benchmarks prove the effectiveness of the proposed flow.

This paper presents a new design flow, FPD-SiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic partitioning, floorplanning, global routing, and timing analysis/budgeting steps, followed by technology remapping and detailed placement of the selected logic clusters. The strength of the approach lies in the dynamic programming-based algorithm, SiMPA-D, used for performing simultaneous technology mapping and linear placement of logic clusters. This algorithm generates a set of solutions for each cluster, all of which are noninferior (in terms of gate area, cutwidth and delay), and hence permits trade-offs between total area (gate plus wiring) and total delay (gate plus wiring). Experimental results from a large number of MCNC benchmarks have proved the effectiveness of the proposed flow.

This paper presents an integrated design flowwhich combines floorplanning, technology mapping, andplacement using a dynamic programming algorithm. Theproposed design flow consists of five steps: maximum treesub-structure formation, levelized cluster tree construction,minimum area implementation using 2-D shape functions,critical path identification, and repeated application ofsimultaneous floorplanning, technology mapping and gateplacement along the timing critical paths. Experimentalresults obtained from an extensive set of benchmarksdemonstrate the effectiveness of the proposed flow.

ABSTRACT- This paper presents an optimal algorithm for solving the problem of simultaneous fanout optimization and routing tree construction for an ordered set of critical sinks. The algorithm, which is based on dynamic programming, generates a rectilinear Steiner tree routing solution containing appropriately sized and placed buffers. The resulting solution, which inherits the topology of LT-Trees and the detailed structure of P-Trees, maximizes the signal required time at the driver of the given set of sinks. Experimental results on benchmark circuits demonstrate the effectiveness of this simultaneous approach compared to the sequential methods. 1.

The authors present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of minimizing the post-layout area. The proposed algorithm relies on the generation of gate-area versus cut-width curves using a dynamic programming approach. A novel design flow which extends this algorithm to minimize the circuit delay and handle general DAG structures is also presented. Experimental results on MCNC benchmarks are reported.