Nicolas Boullis

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4ranked-venue papers

3as first author

0since 2021 · last 2005

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorTheory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 80% Reconfigurable computing and FPGAs · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Electronic design automation › design optimization area-time optimization	0.1	1	2005	Some Optimizations of Hardware Multiplication by Constant Matrices · IEEE Trans. Computers 2005
Electronic design automation › logic synthesis › logic optimization common subexpression elimination	0.1	1	2005	Some Optimizations of Hardware Multiplication by Constant Matrices · IEEE Trans. Computers 2005
Electronic design automation › high-level synthesis constant multiplication	0.1	1	2005	Some Optimizations of Hardware Multiplication by Constant Matrices · IEEE Trans. Computers 2005
Reconfigurable computing and FPGAs FPGA implementation	0.1	1	2005	Some Optimizations of Hardware Multiplication by Constant Matrices · IEEE Trans. Computers 2005
Electronic design automation › high-level synthesis › constant multiplication multiple constant multiplication	0.1	1	2005	Some Optimizations of Hardware Multiplication by Constant Matrices · IEEE Trans. Computers 2005

Methods — techniques the papers use, named apart from their topics

number recoding · 0.1common subexpression factorization · 0.1

Year	Publication	Venue	Position
2005	Some Optimizations of Hardware Multiplication by Constant Matrices abstract This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved. Nicolas Boullis, Arnaud Tisserand	IEEE Trans. Computers	1
2003	Some Optimizations of Hardware Multiplication by Constant Matrices abstract We present some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication (CMM), i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved. Nicolas Boullis, Arnaud Tisserand	IEEE Symposium on Computer Arithmetic	1
2001	Pipelined Function Evaluation on FPGAs Nicolas Boullis, Oskar Mencer, Wayne Luk, Henry Styles	FCCM	1
2001	Parameterized Function Evaluation for FPGAs Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles	FPL	2