This paper describes an online laboratory for a course on electronic devices and circuits aimed at complementing classroom teaching of undergraduate courses. The development is based on four levels of teaching, viz., lecture notes, interactive tutorials, simulation exercises, and performing a real experiment remotely. The current facility has been developed to support an undergraduate theory course, “Electronic Devices and Circuits” as a pre-laboratory session for a regular on-site laboratory. It can be also used as an alternative to a traditional laboratory especially for distance education programs, or for interdisciplinary first year courses not having lab component. The facility has also been developed as a teaching tool for classroom demonstrations.

We present novel and efficient methods for built-in self-test (BIST) of field-programmable gate arrays (FPGAs) for detection and diagnosis of permanent faults in current, as well as emerging, technologies that are expected to have high fault densities. Our basic BIST methods can be used in both online and offline testing scenarios, although we focus on the former in this paper. We present 1- and 2-diagnosable BISTer designs that make up a ROving TEster (ROTE). Due to their provable diagnosabilities, these BISTers can avoid time-intensive adaptive diagnosis without significantly compromising diagnostic coverage-the percentage of faults correctly diagnosed. We also develop functional testing methods that test programmable logic blocks (PLBs) in only two circuit functions that will be mapped to them as the ROTE moves across a functioning FPGA. We extend our basic BISTer designs to those with test-pattern generators (TPGs) using multiple PLBs to more efficiently test the complex PLBs of current commercial FPGAs and to also prove the diagnosabilities of these designs. Simulation results show that our 1-diagnosable functional-test-based BISTer with a three-PLB TPG has very high diagnostic coverages-for example, for a random-fault distribution, our nonadaptive-diagnosis methods provide diagnostic coverages of 96% and 88% at fault densities of 10% and 25%, respectively, whereas the previous best nonadaptive-diagnosis method of the STAR-3 × 2 BISTer has diagnostic coverages of about 75% and 55% at these fault densities.

We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than prior FPGA testing methods. We present 1- and 2-diagnosable built-in self-tester (BISTer) designs that make up the ROTE, and that avoid expensive adaptive diagnosis. To the best of our knowledge, this is the first time that a BISTer design with diagnosability greater than one has been developed for FPGAs. We also develop functional testing methods that test PLBs in only two circuit functions that will be mapped to them (as opposed to testing PLBs in all their operational modes) as the ROTE moves across a functioning FPGA. Simulation results show that our 1-diagnosable BISTer and our functional testing technique leads to significantly more accurate (98% fault coverage at a fault/defect density of 10%) and faster test-and-diagnosis of FPGAs than achieved by previous work. The fault coverage of ROTE is also expected to be high at fault/defect densities of up to 25% using our 1-diagnosable BISTer and up to 33% using our 2-diagnosable BISTer. Our methods should thus prove useful for testing current very deep submicron FPGAs as well as future nano-CMOS and molecular nanotechnology FPGAs in which defect densities are expected to be in the 10% range.

We propose a roving tester (ROTE) that tests the PLBs of the FPGA by periodically moving across it. At any time, the ROTE occupies a certain area of the FPGA, say two columns, and tests all PLBs in that area using parallel built-in self-tester (BISTers). A significant contribution of this work are designs for 1- and 2-diagnosable BISTers. To the best of our knowledge, this is the first time that BISTer designs with provable diagnosabilities have been developed for FPGAs. We also develop functionality-specific testing methods that test PLBs in only two circuit functions that will be mapped to them (as opposed to testing PLBs in all their operational modes), for any reconfigurable fault pattern as the ROTE moves across the FPGA. The combination of our 1- or 2-diagnosable BISTer design and our functionality-specific testing technique leads to more accurate and faster test-and-diagnosis of FPGAs than achieved by previous work.

Incremental physical CAD is encountered frequently in the so-called engineering change order (ECO) process in which design changes are made typically late in the design process in order to correct logical and/or technological problems in the circuit. Incremental routing is a significant part of an incremental physical design methodology. Typically after an ECO process, a small portion of the circuit netlist is changed, and in order to capitalize on the enormous resources and time already spent on routing the circuit it is desirable to reroute only the ECO-affected portion of the circuit, while minimizing any routing changes in the much larger unaffected part. Incremental rerouting also needs to be fast and to effectively use available routing resources. In this article, we develop a complete incremental routing methodology for FPGAs using a novel approach called bump and refit (B&R). The basic B&R idea (which was originally proposed in Dutt et al. [1999] in the much simpler context of extending some nets by a segment for the purpose of fault tolerance) in our algorithms is to rearrange some portions of some existing nets on other tracks within their current channels in order to find valid routings for the new/modified nets without requiring any extra routing resources and with little effect on the electrical properties of existing nets. Here we significantly extend the B&R concept to global and detailed incremental routing for FPGAs with complex switchboxes (SBox's) such as those in Lucent's ORCA and Xilinx's Virtex series. We introduce new concepts such as a B&R cost in global routing and the optimal subnet set to relocate for each bumped net (determined using an efficient dynamic programming formulation). We developed optimal and near-optimal algorithms (called Subsec_B&R and Subnet_B&R, respectively) to find incremental routing solutions using the B&R paradigm in complex FPGAs (e.g., Lucent's ORCA FPGA) with i-to-j SBox's, as well as an optimal version Fullnet_B&R for the VPR architecture from the University of Toronto using the simpler i-to-i SBox's. We compared our algorithms (simply called B&R when no distinction needs to be made between our versions) to two recent incremental routing techniques, Standard (Std) and Rip-up&Reroute (R&R), and to Lucent's A_PAR routing tool and the University of Toronto's VPR router used in complete rerouting modes. Experimental results for the ORCA show that B&R is 10 to 20 times faster than complete rerouting using A_PAR, and that B&R is also nearly 27% faster and yields new nets with nearly 10% smaller lengths compared to previous incremental routers. Furthermore, B&R routers do not change either the lengths or topologies of existing nets, a significant advantage in ECO applications, in contrast to R&R which increases the length of ripped-up nets by an average of 8.75 to 13.6%. Experimental results for the VPR architecture are dominated by the significantly larger (in many cases, orders of magnitude more) number of nets left unrouted by Std and R&R compared to B&R, which highlights the much greater efficacy of B&R-based incremental routing. However, B&R is significantly slower than the other two incremental routers, although on an absolute scale it is quite fast for two of four cases we simulated; in one case, it is about 25 times faster than VPR used in the full rerouting mode. The relative slowness of B&R for the VPR architecture arises from the fact that we used i-to-i SBox's which forces each net to be routed on the same track, thus causing significantly more bumpings and searches for rearranged solutions compared to i-to-j SBox's where a net can be routed on different interconnected tracks to minimize the amount of bumpings (as we did for the ORCA). Since modern FPGAs generally have the latter type of SBox's, B&R would be fast as well as very effective on them.

Incremental physical CAD is encountered frequently in the so-called engineering change order (ECO) process in which design changes are made typically late in the design process in order to correct logical and/or technological problems in the circuit. As far as routing is concerned, in order to capitalize on the enormous resources and time already spent on routing the circuit, and to meet time-to-market requirements, it is desirable to re-route only the ECO-affected portion of the circuit, while minimizing any routing changes in the much larger unaffected part of the circuit. Incremental re-routing also needs to be fast and to effectively use available routing resources. We develop a complete incremental routing methodology for FPGAs using a novel approach called bump and refit (B&R). We significantly extend this concept to global and detailed incremental routing for FPGAs with complex switchboxes such as those in Lucent's ORCA and Minx's Virtex series. We also introduce new concepts such as B&R cost estimation during global routing, and determination of the optimal subnet set to bump for each bumped net, which we obtain using an efficient dynamic programming formulation.

In this paper we present a novel integrated approach to on-line FPGA testing, diagnosis, and fault-tolerance, to be used in high-reliability and high-availability hardware. The test process takes place in self-testing areas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is eventually tested by having (STARs) gradually rove across the FPGA. Our approach guarantees complete testing of programmable logic blocks and interconnect, and provides maximum diagnostic resolution. A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults. We also introduce the basic concepts of a new dynamic FT method, spare resources needed to bypass a fault are always in the neighborhood of the located fault, thus simplifying fault-bypassing.