Proofs in the Nuprl system, an implementation of a constructive type theory, yield "correct-by-construction" programs. In this paper a new methodology is presented for extracting efficient and readable programs from inductive proofs. The resulting extracted programs are in a form suitable for use in hierarchical verifications in that they are amenable to clean partial evaluation via extensions to the Nuprl rewrite system. The method is based on two elements: specifications written with careful use of the Nuprl set-type to restrict the extracts to strictly computational content; and on proofs that use induction tactics that generate extracts using familiar fixed-point combinators of the untyped lambda calculus. In this paper the methodology is described and its application is illustrated by example.

Many aspects of design automation software have similar requirements for representing, manipulating, and storing design information. The recognition of these common requirements in CAD tools, allows the Flexible Architecture Compilation Environment's (FACE) Core Environment to provide a suite of high level tools for the CAD developer. The Core Environment software has been developed using object-oriented software technology, and may be readily adapted to specific applications. The focus of the core environment is to improve the productivity of CAD tool developers through better tool integration and a state-of-the-art software development environment. This Core Environment software has been used in the development of an integrated tool set covering algorithm specification, structural synthesis, and physical assembly of digital hardware systems. The focus of this paper is on the Core Environment's organization and its use in application tool development.

In the past, real-time synthesis has been achieved using either relatively expensive special hardware or custom integrated circuitry which implements a single synthesis algorithm. In order to fill a need for low cost, high quality synthesis with algorithm flexibility, two NMOS LSI devices which implement a programmable speech microprocessor have been developed. By orienting the architecture toward common features of several classes of digital vocal tract models, synthesis computations involving a large number of multiplies, adds, and other operations can be performed efficiently. For example, the processor can implement a complex cascade/parallel formant synthesizer or a lattice filter with up to fourteen poles. The LSI chip set will become commerically available in mid-1980.