The functional safety of implanted medical devices is of high importance. This works presents a novel concept to verify bio-electronic systems modeling the medical device in connection with the interacting biological system. The concept is applied to a setup consisting of an implanted pacemaker and an interacting organ, the human heart. The resulting model is verified with respect to relevant properties such as the reachability of hazard-related states appearing through the interaction of the bio-electronic system. In contrast to previous contributions this work demonstrates the ability to deterministicly verify bio-electronic systems containing relevant and detailed models of the interacting biological system.

This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.

The saturation of the IJTAG concept and its approval as the IEEE 1687 standard in 2014 has generated a wave of research activities and created demand for a set of appropriate and challenging benchmarks. This paper presents such a set developed by an industrial and academic consortium and constructed in a way that facilitates objective comparison of experimental results across research groups as well as represents challenging network examples exhaustively utilizing features and constructs defined by the standard. The suite is arranged in four comprehensive categories, each having its particular purpose and composition principles, as described in the paper. We have also made an analysis of limitations of previous popular and ad-hoc benchmark sets as these limitations majorly motivated our current action. The new public-domain benchmarks are distributed together with source files and documentation through the dedicated web site. Some of the previous research results on IEEE 1687 have been reapplied on the new benchmarks set, thus creating an important initial reference point for the research community.

IEEE 1687 enables flexible access to on-chip instruments via dynamically reconfigurable networks. Reconfiguration allows reducing instrument access time by keeping only those instruments on the scan-path which are required for each access. To perform reconfiguration and execute commands described in instrument access procedures, scan vectors are generated in a process called retargeting. These vectors are then applied through a number of capture-shift-update (CSU) operations. Generating the optimal set of vectors w.r.t. application time is modeled as an Integer Linear Optimization Problem, which is an NP-hard problem. In the modeling, an IEEE 1687 network is represented as a sequential problem unrolled over a number of time frames, each frame corresponding to a CSU operation. A key challenge is to find the number of required CSU operations, which should be sufficiently high so that the optimal solution is included in the search space but kept as low as possible to keep the model less complex and thus suitable for large IEEE 1687 networks. In this work, we propose a method to compute an upper-bound on the number of required CSU operations. Through experiments, we show that our method results in a tight upper-bound, is applicable to a large variety of IEEE 1687 network designs, and is able to handle large designs.

Test compaction is an important aspect in the post-production test since it is able to reduce the test data and the test costs, respectively. Current automatic test pattern generation (ATPG) methods treat all faults independently from each other which limits the test compaction capability. We propose a new optimization satisfiability (SAT)-based ATPG for compact test set generation with high fault coverage as well as a new retargeting stage for test set reduction. The ATPG is based on a novel multiple-target test generation formulation using optimization techniques. Robust SAT-based solving algorithms are leveraged to determine compatible fault groups which can be detected by the same test. The proposed technique can be used during initial compact test generation as well as a post-process to increase the compactness of existing test sets, e.g., generated by commercial tools, in an iterative manner. Experimental results show that the proposed SAT-based approach is able to produce highly compacted test sets with high fault coverage for stuck-at as well as transition faults. The approach is able to produce lower pattern counts than a commercial ATPG tool. For one industrial circuit, the test set size can even be reduced down to 26% of the size generated by a commercial ATPG tool.

IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and in-field test. At any of these scenarios, the instruments are accessed differently, and at a given scenario the instruments are accessed differently over time. It means the IEEE 1687 network needs to be frequently reconfigured from accessing one set of instruments to accessing a different set of instruments. Due to the need of frequent reconfiguration of the IEEE 1687 network it is important to (1) minimize the runtime for the algorithm finding the new reconfiguration, and (2) generate scan vectors with minimized access time. In this paper we model the reconfiguration problem using Boolean Satisfiability Problem (SAT). Compared to previous works we show significant reduction in run-time and we ensure minimal access time for the generated scan vectors.

IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

Test compaction is an important aspect in the postproduction test since it is able to reduce the test data and the test costs, respectively. Current ATPG methods treat all faults independently from each other which limits the test compaction capability. This paper proposes a new optimization based SAT-ATPG for compact test set generation. Robust solving algorithms are leveraged to determine fault groups which can be detected by the same test. The proposed technique can be used during initial compact test generation as well as a post-process to increase the compactness of existing test sets, e.g, generated by commercial tools, in an iterative manner. Experimental results on industrial circuits and academic benchmarks show that this technique is able to significantly reduce the pattern count down to 40% for the initial test generation and down to 30% for the iterative reduction.

Numerous new multi-conditional fault models have been proposed in the last years. In combination with the increasing complexity of today's designs these new fault models cause a tremendous increases of the ATPG-runtime. In this paper we present a novel fault collapsing scheme for multi-conditional faults. The objective is to significantly reduce the fault set and hence reduce runtime for ATPG and fault diagnosis. The collapsing technique consists of three individual collapsing stages, which are individually discussed and evaluated. Additionally we provide an extensive set of experimental results including runtimes of a state-of-the-art ATPG-tool applied on a set of large industrial designs. We will demonstrate that the achieved reduction of up to 48% of the number of faults also reduces the ATPG runtime significantly.

This paper focuses on an industrial application of the proposed 1687 standard to significantly improve the test development effort and quality of test patterns for mixed signal IPs of an automotive design. The P1687 standard will enable the industry to develop test patterns for IPs on the IP level without having to know how the IP will be embedded within different designs. To measure the impact of P1687, we are applying a commercial P1687 EDA tool on an industrial 65nm automotive design. The presented results underline the significant advantages of P1687 over the current IEEE Std 1149.1-based test methodology, in both, automation of test pattern development as well as reduction of test setup data volume by more than 50%.

The test set size is a highly important factor in the post-production test of circuits. A high pattern count in the test set leads to long test application time and exorbitant test costs. We propose a new test generation approach which has the ability to reduce the test set size significantly. In contrast to previous SAT-based ATPG techniques which were focused on dealing with hard single faults, the proposed approach employs the robustness of SAT-solvers to primarily push test compaction. Furthermore, a concept is introduced how the novel technique can be flexibly integrated into an existing industrial flow to reduce the pattern count. Experimental results on large industrial circuits show that the approach is able to reduce the pattern count of up to 63% compared to state-of-the-art dynamic compaction techniques.

This paper presents a highly robust approach to exactly analyze signal probabilities of Weighted Random Logic (WRL) BIST structures. WRL BIST structures are implemented in modern CMOS designs to ensure high defect coverage for example during on-line in-system tests, which are executed periodically in safety applications as needed in automotive designs. Furthermore the paper describes a novel design flow which automatically identifies and evaluates WRL BIST structures in large industrial designs. The complete design flow from calculating the weighted random logic up to its automatic identification and evaluation in pre- and post-layout netlists is discussed in detail. The effectiveness of the new approach has been evaluated on 10 industrial designs and various other test cases. The results show that the memory consumption of the proposed technique does not grow despite of an immense increase of the circuit size.

It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially on large industrial circuits. These circuits usually contain a lot of functional redundancy which, on the one hand, is often needed during operational mode, but on the other hand, causes dispensable overhead during ATPG. Using the traditional circuit-to-CNF transformation, this redundancy is also contained in the SAT instances. The contribution of this paper is a new technique to improve the SAT instance generation for SAT-based ATPG. The objective of the proposed method is to use Binary Decision Diagrams (BDDs) to optimize the resulting CNF representations. In order to apply the proposed technique to industrial circuits, we developed dedicated BDD operations using a multiple-valued logic. The experimental results, obtained on large industrial designs, show that the accomplished optimizations result in a considerable acceleration of the overall ATPG runtime as well as in a significant reduction of the unclassified faults.

Industry is facing very high quality requirements for today's and tomorrow's ICs. Especially in the automotive market these quality requirements need to be fulfilled. To achieve this we need to improve currently used test methods and fault models to improve the overall defect coverage. This paper presents two new methodologies to significantly improve this situation. One method will focus on cell-internal Bridges over a wide range of Bridge resistor values and the second method concentrates on library cell-internal high-resistive Open defects. The fault models used during the ATPG are enhanced to directly target the layout-based intra-cell Open and Bridge defects. Both methods have been evaluated on 1500 library cells of a 65nm technology. In addition the wide range of intracell Bridges has been evaluated on 10 real industrial designs with up to 60 million faults. Various results are presented from all 1500 library cells and from the 10 industrial designs as well.

Industry is facing increasingly tougher quality requirements for more complex ICs. To meet these quality requirements we need to improve the defect coverage. This paper presents a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults. In contrast to previous techniques, such as gate-exhaustive, N-detect, or embedded-multi-detect, which either are too complex for real-world designs or merely improve the probability of detecting intra-cell defects, the new approach targets the actual root causes of intra-cell defects. The newly proposed cell-aware-methodology has been evaluated for 90 nm and 65 nm technologies on 1671 library cells and on 10 real industrial designs with up to 50 million faults. The experimental results show an average increase of 1.2% in defect coverage and a reduction of 420 ppm in escape rate for a 50 mm2design.

Despite the recent advances in ATPG technology computing test patterns for state-of-the-art industrial designs can demand an enormous amount of computation time. Numerous structural techniques were presented to reduce the search space and hence the runtime of state-of-the-art ATPG tools. Absolute dominators introduced by Kirkland and Mercer proved to be useful for finding mandatory observation nodes in a combinational circuit. A mandatory observation node denotes a gate which must be visited in order to propagate a fault to at least one primary output. Unfortunately their algorithm to compute absolute dominators does not scale well on large industrial designs. In this paper we propose a new algorithm to find absolute dominators in circuit graphs. The experimental results show a significant performance improvement with respect to runtime and memory consumption. The achieved speedup of three orders of magnitude on several designs enables the computation of absolute dominators in large industrial circuits in less than a second.