A linear system with time-delay which varies with time is considered as a plant. A feedback structure which uses only the instantaneous internal variables is assumed, and the feedback gain is determined with a solution of some matrix inequalities. It is shown that the resulting closed loop system is asymptotically stable, and moreover, it is the optimal regulator minimizing a quadratic cost functional, which contains time-varying weights. The required solution of the matrix inequalities can be calculated with a solution of some linear matrix inequalities, which can be solved numerically. A numerical example is shown to demonstrate the design procedure.

This paper describes incremental logic synthesis for supporting function logic changes in the physical design stage of digital systems. The incremental logic synthesis is distinguished from logic synthesis in the respect that it updates only gate logic components, which must be changed due to the function logic changes, in the physically optimized gate logic structure. For making the incremental logic synthesis feasible, a gate logic structure identification and editing system has been developed with a corresponding gate matrix method as its core. This system has greatly contributed to the increase in design efficiency of the very large computer series M68XH.