Adversarial examples are slightly modified inputs devised to cause erroneous inference of deep learning models. Protection against the intervention of adversarial examples is a fundamental issue that needs to be addressed before the wide adoption of deep-learning based intelligent systems. In this research, we utilize the method known as input recharacteri-zation to effectively eliminate the perturbations found in the adversarial examples. By converting images from the intensity domain into density-based representation using half toning operation, performance of the classifier can be properly maintained. With adversarial attacks generated using FGSM, I-FGSM, and PGD, the top-5 accuracy of the hybrid model can still achieve 80.97%, 78.77%, 81.56%, respectively. Although the accuracy has been slightly affected, the influence of adversarial examples is significantly discounted. The average improvement over existing input transform defense mechanisms is approximately 10%.

In recent years, thermal management, which improves the reliability, performance, power leakage, etc. of modern microprocessors, has been the subject of numerous computer architecture and system software studies. To determine the detailed thermal distribution of a microprocessor is among the critical tasks for thermal management. However, because thermal modeling tools require considerable computation time and memory to simulate fine-grain thermal information, they may be unsuitable for dynamic thermal management and hardware implementation. This study proposes a novel model based on reduced resistance-capacitance (RC) networks for efficiently calculating the temperature of a microprocessor. The proposed model is compared with two existing thermal simulation tools, namely, HotSpot [1] and Temptor [2]. The experiment studies show that the results generated using the proposed model differ from those of the existing tools by only 0.5 to 1.5%. However, the suggested model can increase computation speeds by 5 to 9 times and 98 to 161 times that of Temptor and HotSpot, respectively. For the memory usage, the proposed model consumes merely 0.45% of the space used by the existing tools.

Multimedia playback programs must satisfy certain hard real-time constraints to give their user a pleasant viewing experience. Having a tight estimation on the worst case execution time (WCET) is essential for the resource scheduler to ensure all the tasks in the system can satisfy their timing requirements while maintaining good system resource utilization. In this paper we present a detailed hybrid WCET analysis of the H.264/AVC reference decoder and demonstrate that the coding information can be used to tighten the pure static WCET estimation up to 70%.

Code repositioning is a well-known method of reducing inefficient off-chip memory accesses by streamlining cache behavior. Embedded systems with predetermined applications can achieve further improvement with the addition of fast and energy efficient scratchpad memory (SPM) on chip and moving frequent accesses code and/or data from main memory to SPM. While many researchers have attempted to either streamline cache accesses or improve the effectiveness of SPM, few studies focus on exploring their joint synergy. This study proposes integer linear programming (ILP) models that include both code repositioning and SPM code selection to identify the optimal code layout and reduce energy consumption in embedded systems with a cache and SPM. This study also proposes a two-stage metaheuristic algorithm. Experimental results reveal that 1) allocating a dedicated portion of the on-chip SRAM to the SPM is not always better than using a cache-only configuration and 2) it is not trivial to select code objects for the SPM. As much as 55 percent additional energy can be saved by applying both code repositioning and SPM code selection techniques.

A Δ-Σ fractional-N Phase-locked Loops (PLL)- based frequency synthesizer (FS) with a frequency range of 250 MHz to 4 GHz is presented. By employing the Δ-Σ fractional-N technique and utilizing the multi-phase clocks available in the ring-VCO of the PLL, the frequency synthesizer is capable of generating high-resolution and low-spur clocks with instant frequency switching. Moreover, the proposed FS has the ability to adjust clock duty cycle which is needed in applications such as time-interleaved ADCs, switched-capacitor circuits, and DC-DC converters.

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, Fractional-N architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is based on a new concept, Time-Average-Frequency, to generate frequencies. This paper presents an in-depth analysis and comparison between the two methods.

In grid routing, the plane is tessellated into equal-sized square cells.Two cells are called neighbor cells if they share a common edge, and two nodes are called routing neighbors if they are in neighbor cells and within each other's transmission range.If communication parties are in the same cell, packets can be transmitted directly; otherwise, packets are forwarded to routing neighbors that are in cells closer to destination cells.As a greedy strategy, grid routing suffers the existence of local minima at which no neighbor nodes exist for relaying packets.To guarantee deliverability, in this paper, we investigate two vital parameters of grid routing, called the grid size and the transmission radius.Assume that nodes are represented by a Poisson point process with rate n over a unit-area square, and let l denote the grid size and r the transmission radius.First, we show that if l = β ln n/n for some constant β and r = √ 5l, then β = 1 is the threshold for deliverability.In other words, there almost surely do not exist local minima if β > 1 and there almost surely exist local minima if β < 1. Next, for any given β > 1, we give sufficient and necessary conditions to determine the critical transmission radius (CTR) for deliverability.Then, we show that as β ∼ = 1.092, the CTR r ∼ = 2.09 √ ln n/n is the minimum over all β > 1. Simulation results are given to validate this theoretical work.

A frequency synthesizer architecture with a wide tuning range and reduced fractional spurs is presented. The proposed topology includes a Σ-Δ fractional-N synthesizer and an integer Flying-Adder architecture. Compared to the conventional Σ-Δ fractional-N frequency synthesizer, this approach has much wider tuning range. Compared to the fractional Flying-Adder frequency synthesizer, the proposed approach can achieve the same frequency resolution with reduced fractional spurs and alleviates the constraints on the adder design in the Flying-Adder architecture.

The Flying Adder (FA) architecture is one of the latest developments in the area of on-chip frequency synthesis. It has two operating modes: integer-FA mode and fractional FA mode. In the fractional FA mode, a concept of Time-Average-Frequency is used to synthesize certain frequencies that cannot be easily obtained using traditional methods. The issue of using Time-Average-Frequency to drive digital systems has been studied in previous publications by the authors. In this paper, we investigate the impact of using Time-Average-Frequency based clock signals to drive systems with embedded Digital-to-Analog Converters (DAC).