Resistance-inductance-capacitance (RLC) network reduction refers to the formulation of small networks whose port behavior is similar to that of large RLC networks. Several network reduction algorithms have been developed in the last few years, but none exist for RLC networks which preserve passivity. The loss of passivity can be a serious problem because simulations of the reduced networks may encounter artificial oscillations or "time step too small" errors which render the simulations useless. This paper presents a set of well-conditioned transformations called "split congruence transformations" (SCTs) which can he used to preserve specified moments and resonances for RLC network reduction, and these transformations are proven to preserve passivity. Network reduction examples are provided to demonstrate the utility of SCTs.

None of the existing network reduction tools preserve passivityfor RLC networks. The loss of passivity can be a serious problembecause simulations of the reduced networks may encounter"time step too small" errors. This paper presents a set oftransformations called "Split Congruence Transformations"(SCT's) which can be used to accurately reduce a RLC networkwhile preserving passivity.

A novel technique is presented which employs pole analysis via congruence transformations (PACT) to reduce RC networks in a well-conditioned manner. Pole analysis is shown to be more efficient than Pade approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks. The error incurred by reducing the networks is shown to be bounded by values which are fully selectable by the user. Networks are represented by admittance matrices throughout the analysis, and this representation both simplifies interfacing the reduced networks with circuit simulators and facilitates realization of the reduced networks using RC elements. A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm.

A novel technique is presented which employs Pole Analysis via Congruence Transformations (PACT) to reduce RC networks in a well-conditioned manner.Pole analysis is shown to be more efficient than Padé approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks.Networks are represented by admittance matrices throughout the analysis, and this representation simplifies interfacing the reduced networks with circuit simulators as well as facilitates realization of the reduced networks using RC elements.A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm.

Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal integrated circuits. In particular signal cross talk through the common chip substrate has become increasingly problematic. The paper demonstrates a new methodology for developing simulation, synthesis, and verification models to analyze the global electrical behavior of the non-ideal semiconductor substrate. RC substrate network models, which are generated via a triangular discretization method, are accurately approximated for subsequent analysis by an efficient reduction algorithm. This algorithm utilizes the well-conditioned Lanczos process to formulate Pade approximations of the network port admittance. Congruence transformations are employed to ensure stability, and to create reduced networks which are easily realizable with SPICE-compatible RC elements. For validation, the strategy has been successfully applied to several mixed-signal circuit examples.