Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Jovanka Ciric

dblp:38/3840 · DBLP profile ↗
← Back
3ranked-venue papers
3as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis
boolean matching		 0.012003
Efficient canonical form for Boolean matching of complex functions in large libraries · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Electronic design automation › logic synthesis › boolean function representation
canonical form		 0.012003
Efficient canonical form for Boolean matching of complex functions in large libraries · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Electronic design automation
logic synthesis		 0.012003
Efficient canonical form for Boolean matching of complex functions in large libraries · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003
Electronic design automation › logic synthesis
technology mapping		 0.012003
Efficient canonical form for Boolean matching of complex functions in large libraries · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003

Methods — techniques the papers use, named apart from their topics

truth table canonicalization · 0.0hash table lookup · 0.0
YearPublicationVenuePosition
2003 Efficient canonical form for Boolean matching of complex functions in large libraries
abstract
A new algorithm is developed which transforms the truth table or implicant table of a Boolean function into a canonical form under any permutation of inputs. The algorithm is used for Boolean matching for large libraries that contain cells with large numbers of inputs and implicants. The minimum cost canonical form is used as a unique identifier for searching for the cell in the library. The search time is nearly constant if a hash table is used for storing the cells' canonical representations in the library. Experimental results on more than 100000 gates confirm the validity and feasible runtime of the algorithm.
Jovanka Ciric, Carl Sechen
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2001 Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries
abstract
A new algorithm is developed which transforms the truth table or implicant table of a Boolean function into a canonical form under any permutation of inputs. The algorithm is used for Boolean matching for large libraries that contain cells with large numbers of inputs and implicants. The minimum cost canonical form is used as a unique identifier for searching for the cell in the library. The search time is nearly constant if a hash table is used for storing the cells' canonical representations in the library. Experimental results on more than 100,000 gates confirm the validity and feasible run-time of the algorithm.
Jovanka Ciric, Carl Sechen
 ICCAD1
2000 Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic
abstract
This paper presents a new delay minimization and technology mapping algorithm for two-level structures (TLS) implemented using clock-delayed (CD) domino logic. We take advantage of CD domino's high-speed, large fan-in NOR and OR gates to increase the speed of a circuit by partial collapsing. The algorithm is delay-driven and the delays are obtained from a characterized CD domino library. The results on eight combinational MCNC benchmark circuits show an average speed improvement of 89% for CD domino with TLS, compared to static CMOS implementations generated by Synopsys. CD domino with TLS using our tools produced on average 44% faster circuits than CD domino benchmarks minimized and mapped using Synopsys. The delay results for CD domino with TLS were on average 22% better than for standard domino.
Jovanka Ciric, Gin Yee, Carl Sechen
 DATE1