As the behavior of user comment brushing on e-commerce and social platforms becomes increasingly hidden, this article constructs a detection algorithm that integrates dynamic graph neural network (dynamic GNN) and federated learning to detect the blind spots caused by deep learning-generated text and cross-platform collaborative brushing. Dynamic GNN is used to model user-device temporal associations to identify group topological features, and federated learning is used to aggregate multiplatform features to improve cross-platform detection performance while protecting privacy. Based on user comment behavior sequences, such as device ID (identifier), IP (Internet protocol), and timestamp, a dynamic heterogeneous graph (nodes: users/devices; edges: interaction frequency and time series) is constructed, and the topological structure is updated through a sliding window to capture short-term collaborative brushing patterns. A time-aware graph attention mechanism is adopted to aggregate the historical states of neighbor nodes and the current interaction features and output the temporal embedding vector of the user node to characterize its membership in the brushing group. Each platform trains the dynamic GNN model locally, and the central server aggregates cross-platform features such as device fingerprints and IP geographic distribution through federated averaging (FedAvg) to avoid the sharing of raw data. The user temporal embedding is concatenated with the federated features and input into the multilayer perceptron (MLP). The probability of user brushing is output, and the suspicious groups are marked after the threshold is determined. Experimental results show that the dynamic GNN integrated with federated learning has a false alarm rate of 12.1% and an F1-score of 83.1% under an attack density of 50%, demonstrating high cross-platform detection performance. When the time window changes from 30 to 600 s, the mean feature update delay decreases linearly with the increase of the window (38.2→15.9 ms), maintaining a millisecond-level response. The changing trend of the mean training throughput (12 450→29 450 edges/s) directly reflects the elastic expansion capability of the model architecture and has a high dynamic topology capture timeliness. The experimental data verify the effectiveness of this article’s research on the algorithm for identifying user comment brushing behavior.

This paper presents a power-efficient fourth-order, 50-MHz active-RC filter with high dynamic range (DR). Unlike conventional Tow-Thomas biquads, the proposed design employs a passive integrator as the second pole to reduce power consumption, enhance noise performance, and facilitate frequency compensation. The active integrator features a two-stage operational transconductance amplifier (OTA) with a push-pull output, ensuring linearity and reducing the OTA’s gain requirements. Fabricated in standard 0.18-μm CMOS technology, the proposed filter achieves an in-band (IB) input third-order intercept point (IIP3) of +29.9 dBm at 30 MHz and an input-referred IB integrated noise of 163.8 μVRMS, while consuming 5.4 mW for a 50-MHz bandwidth.

A 50 MHz bandwidth (BW) transimpedance ampli-fier (TIA) is designed for 5G Sub-6GHz SAW-less current-mode receivers (RX). It's based on an operational transconductance amplifier (OTA). To tolerate blockers, the TIA must exhibit excellent in-band (IB) and out-of-band (OOB) linearity, which in turn requires OTAs with high BW and gain. Traditional two-stage OTAs struggle to achieve this under low power consumption (PC), so this paper employs a three-stage OTA. A pseudo-differential structure without the tail current source is used to accommodate low supply voltages (Vdd). Differential-mode (DM) stability relies on feedforward (FF) compensation within the OTA and zero compensation in the feedback network. Common mode (CM) is stabilized by five different common mode rejection (CMR) techniques. The circuit is designed and simulated in a 40 nm low power (LP) CMOS technology with a Vdd of 1.2V. The post-layout simulation results show that when IM3 is set to 30 MHz, the TIA's IB and OOB IIP3 reach 31.6 dBm and 50.6 dBm, respectively. The minimum input-referred noise (IRN) is 5.14$\mathbf{nV}/\sqrt{Hz}$. The corresponding FoM value is as high as 186.3 dBJ-1, exceeding all previous designs. The chip consumes 10.4 mW of power and occupies only 0.016mm2.

A wideband LNTA based on cascode inverters is presented, suitable for 5G Sub-6GHz applications. Cascode technique improves the bandwidth, reverse isolation and output impedance. Noise canceling(NC) technology and the new derivative superposition method are adopted to achieve better noise and linearity, respectively. Intrinsic second-order input impedance and off-chip L-type and T-type matching networks are utilized to increase the S11 bandwidth. The use of MOSFETs with different threshold voltages(Vth) simplifies the bias circuit. The first stage of the LNTA is a shunt-shunt feedback LNA, where the feedback resistance Rfaffects the four key performances of gain, bandwidth, noise and linearity. By adjusting the value of Rf, the LNTA can work either in low noise(NF mode) or high linearity(IIP3 mode). The LNTA is designed under the TSMC40nmLP process, and the post-layout simulation shows that the noise figure(NF) can be as low as 1. 52dB under the NF mode. The IIP3 and PldB can reach 10. 58dBm and -1.46dBm respectively under the IIP3 mode. The overall power consumption is only 15. 49mW. The chip core has no inductors and capacitors, making its area only 0.0026mm2.

This paper presents a 4th-order active-RC low-pass filter (LPF) with tunable cut-off frequency (20-50 MHz). To achieve high in-band linearity performance, a three-stage opamp with an operational transconductance amplifier (OTA) output stage is adopted. The first two stages of the opamp only introduce about 45° phase shift using Miller-feedforward hybrid compensation scheme, which guarantees the stability of the filter. The designed opamp can achieve 47 dB gain and 1.4 GHz gain-bandwidth products (GBW) for the filter with 50 MHz cut-off frequency. The post-layout simulation results show that the filter consumes 5.7 mW from 1.1 V supply voltage. The in-band integrated input-referred noise (IRN) is 473 μVrms. The filter achieves 29.8 dBm IIP3 at 30 MHz. Due to the high in-band linearity performance, 153.4 dB · J-1of figure-of-merit is achieved in this design.

Nanopore-based DNA sequencing technology has become one of the most promising sequencing approaches with its advantages of label-free and low cost. However, most of the biosensor systems for nanopore sequencing only perform passive detection which is merely part of the overall function of a practical DNA sequencing platform. In this paper, a multifunctional automated integrated CMOS platform for nanopore-based DNA sequencing is presented. The platform equipped with 16*8 biosensor array for nanopore detection is also able to perform bilayer lipid membrane capacitance detection and nanopore insertion pulse generation, realizing the whole process automated auxiliary function from transducer preparation to DNA sequencing. Post layout simulation shows that each cell consumes only 37.366μW while the whole system occupying 1.633mm2.