EDBT 2026 Demo / reviewers in the wild / expert
Toru Chiba
dblp:38/440
· DBLP profile ↗
8ranked-venue papers
1as first author
0since 2021 · last 1997
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 1 first-authorComputer networks · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
Electronic design automation · 98% Integrated circuit design · 2% |
Topics — the 10 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 5 | 1983 | An Automatic Routing Scheme for General Cell LSI · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 A placement algorithm for polycell LSI and ITS evaluation · DAC 1982 SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Electronic design automation › physical design
routing |
0.0 | 3 | 1983 | An Automatic Routing Scheme for General Cell LSI · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 A placement algorithm for polycell LSI and ITS evaluation · DAC 1982 An automatic routing system for high density multilayer printed wiring boards · DAC 1980 |
Electronic design automation › physical design › routing
detailed routing |
0.0 | 1 | 1983 | An Automatic Routing Scheme for General Cell LSI · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design › routing
global routing |
0.0 | 1 | 1983 | An Automatic Routing Scheme for General Cell LSI · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design
placement |
0.0 | 1 | 1982 | A placement algorithm for polycell LSI and ITS evaluation · DAC 1982 |
Electronic design automation › physical design › layout analysis
hierarchical layout analysis |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Electronic design automation › physical design
layout system |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Electronic design automation › physical design › VLSI layout
printed wiring board layout |
0.0 | 1 | 1980 | An Approach to Gate Assignment and Module Placement for Printed Wiring Boards · IEEE Trans. Computers 1980 |
Integrated circuit design
VLSI design |
0.0 | 1 | 1981 | SHARPS: A hierarchical layout system for VLSI · DAC 1981 |
Electronic design automation › physical design
wiring and routing |
0.0 | 1 | 1980 | An Approach to Gate Assignment and Module Placement for Printed Wiring Boards · IEEE Trans. Computers 1980 |
Methods — techniques the papers use, named apart from their topics
net ordering · 0.0grid-free routing · 0.0placement algorithm · 0.0iterative improvement · 0.0hierarchical layout · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1997 | Low power architecture for high speed infrared wireless communication systemabstractA high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture 4PPM (4-Pulse Position Modulation) infrared signals detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a 1-bit digital demodulator. To extend the range of the link length, a 4PPM demodulator is synthesized to implement a demodulation algorithm which is constructed so as to accommodate the output tolerance of the infrared receiver. A experimental results show that the proposed 4 Mbps infrared communication system can achieve an error free link in the range of 0-140 cm at power consumption of 245 mW and 65 mW for transmitting and receiving, respectively. The communication controller is integrated in a 0.6 /spl mu/m CMOS standard-cell chip, which contains 10,015 transistors on a 12 mm/sup 2/ die. Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba |
ISLPED | 5 |
| 1997 | ASK digital demodulation scheme for noise immune infrared data communication
Hiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba |
Wirel. Networks | 5 |
| 1995 | Synthesis and simulation of digital demodulator for infrared data communicationabstractNo abstract available. Hiroshi Uno, Toru Chiba, Keiji Kumatani, Isao Shirakawa |
ASP-DAC | 2 |
| 1983 | An Automatic Routing Scheme for General Cell LSIabstractAn automatic routing scheme intended dedicatedly for general cell LSI is described, which is constructed of a number of algorithms such as for net ordering, global routing, and detailed routing. This scheme is distinctive in that channel constraint loops are broken automatically at the stage of global routing, and a grid-free routing scheme is employed at the state of detailed routing. The routing program based on this scheme has been incorporated into a design system for LSI which is at work in practice. A part of implementation results are also shown. Sieji Kimura, Noboru Kubo, Toru Chiba, Ikuo Nishioka |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1982 | A placement algorithm for polycell LSI and ITS evaluation
Takashi Kambe, Toru Chiba, Seiji Kimura, Tsuneo Inufushi, Noboru Okuda, Ikuo Nishioka |
DAC | 2 |
| 1981 | SHARPS: A hierarchical layout system for VLSI
Toru Chiba, Noboru Okuda, Takashi Kambe, Ikuo Nishioka, Tsuneo Inufushi, Sieji Kimura |
DAC | 1 |
| 1980 | An automatic routing system for high density multilayer printed wiring boardsabstractRecent advances in the packaging technology of microelectronics have changed the design rules for printed wiring boards (PWB's) such that the number of wiring tracks between adjacent pins of an ordinary dual in line package (DIP) is allowed to be two or more, and the number of signal layers to be laminated is often required to be four or more. When the packaging density or scale of a PWB augments to such an extent, conventional routing schemes are confronted with various difficulties. Ikuo Nishioka, Takuji Kurimoto, Hisao Nishida, Seiji Yamamoto, Toru Chiba, Toshiaki Nagakawa, Takatsugu Fujioka, Masashi Uchino |
DAC | 5 |
| 1980 | An Approach to Gate Assignment and Module Placement for Printed Wiring BoardsabstractHigh-density packaging is one of the most urgent requirements in the design of digital systems. In the assembly of such systems, printed wiring boards (PWB's) are used very often to provide the necessary interconnection among circuit modules. Thus, methods to raise wirability of routers are continually under investigation. Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Toru Chiba, Isao Shirakawa, Hiroshi Ozaki |
IEEE Trans. Computers | 4 |