The increase in memory cell density and capacity has resulted in more faulty cells, necessitating the use of redundant memory row and column lines for repairs. However, existing redundancy analysis (RA) algorithms face a critical issue that RA time increases exponentially with the number of faulty cells. Furthermore, RA solutions for multiple memory chips cannot be derived simultaneously. In this study, a novel RA method is proposed using a convolutional neural network (CNN). The proposed RA algorithm also includes preprocessing to improve training accuracy. The solution locations on the fault map are predicted using multi-label classification. Moreover, parallel solution decision methods ensure that even if the CNN does not find the correct RA solution, an accurate final solution can still be derived, and PyCUDA is used to process multiple memories in parallel. From the experimental results, the normalized repair rate of the proposed RA is 100%. The RA time of the proposed RA is not affected by the number of faults but rather by the CNN execution time. Moreover, RA solutions for multiple memories can be quickly derived simultaneously by utilizing GPU parallel processing. In conclusion, a high yield and low test cost can be achieved.

Test-point insertion (TPI) is an effective technique for improving the random pattern testability of digital circuits. However, it introduces area and performance overhead. Because the test-point area takes a significant portion of the test logic area, many techniques have been studied to reduce the area impact, such as sharing a control point (CP) driver with multiple CPs or replacing a dedicated CP driver with an existing flip-flop. This article proposes shared point insertion for area overhead reduction (SPAR) to simultaneously reduce the area impact of CPs and observation points (OPs). SPAR inserts a shared point instead of inserting a pair of CP and OP individually. Consequently, the pair of CP and OP is provided requirements, such as a control signal or propagation path from each other through the shared point—accordingly, the shared point simultaneously functions as the CP and OP. Furthermore, a signal that drives a shared point can be chosen to ensure the fair propagation of faults. The proposed flow searches for appropriate CP–OP pairs to insert shared points while avoiding potential issues from the newly created path. Experimental results on benchmarks demonstrate that SPAR can significantly reduce area overhead caused by test points while achieving almost identical or even slightly improved test coverage.

Three-dimensional integrated circuits (3-D ICs) utilizing through-silicon via (TSV) technology have many advantages over 2-D ICs, including high bandwidth, high density, and low power consumption. However, TSV, which is a key feature of 3-D ICs, has not only problems due to defects in the manufacturing process but also potential problems due to aging. Various solutions have been proposed to address each of these issues, but no one solution has been proposed considering both. In practice, to improve the overall reliability of the TSV, the two problems should be solved together, not separately. In this article, a new TSV architecture is proposed to cope with both issues. The proposed TSV architecture uses redundant TSVs (RTSVs) to repair faulty TSVs due to manufacturing defects and uses unused RTSVs in this way to solve the aging-related problems. Experimental results show that the proposed architecture achieves similar repair rate with less than 1% difference in less than six clustered faults using smaller hardware overhead, and also shows that unused RTSVs are available with a 98.5% high probability, resulting in a 1.5 times improvement in lifetime.

Three-dimensional integrated circuits (3-D ICs), which feature many benefits, such as high bandwidth and a high degree of integration, have recently received considerable attention from the semiconductor industry. However, these chips feature through-silicon vias (TSVs), which vertically connect multiple dies, and these TSVs may fail, resulting in a decreased yield. Unfortunately, previously proposed methods to repair TSVs cannot handle certain failure patterns. For example, existing techniques cannot repair clustered TSV faults, which commonly occur in practice. Furthermore, the number of signal TSVs typically determines the number of redundant TSVs, which may result in wasteful and redundant TSVs. In this paper, a new TSV repair scheme is proposed that replaces defective TSVs with redundant TSVs by utilizing the architecture of a cube, which can replace any face with any of the other faces. Both signal TSVs and redundant TSVs are placed in the face of cube, so any faulted TSVs can be replaced with redundant TSVs. The experimental results indicate that the new method guarantees 100% coverage with any number of signal TSVs and redundant TSVs.

The poor quality of the die stacking process for 3-D integrated circuits can result in the failure of the process in the through-silicon-vias (TSVs) in dense regions. Previous works use the same number of redundant TSVs and architectures that do not consider the TSV density. A repair architecture and an appropriate number of redundant TSVs, which are chosen considering the TSV density, are required for an improved repair rate. This paper proposes a method that demonstrates such an architecture and calculates the required number of TSVs. The method has a high repair rate for clustered faults, and wire-length problems are solved using the shift-based repair method.

A three-dimensional (3-D) integration technology involving the use of a through-silicon-via (TSV) offers advantages such as low power consumption, small form factor, and large bandwidth. However, owing to the incompleteness of the 3-D manufacturing process, TSVs may exhibit some inherent defects; hence, switching and shifting repairing methods have been proposed. These methods repair the TSV faults by rerouting the signals of the faulty TSVs to the other signal TSVs or redundant TSVs using a simple repair algorithm. However, if one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the FTSV increases, i.e., the TSV defects tend to be clustered. Therefore, recently proposed repair solutions, such as ring/router-based repair architectures, have focused on clustered TSV faults. However, the implementation of these existing repair solutions for clustered faults involves an extremely high hardware overhead. This study proposes a TSV redundancy architecture to repair clustered TSV faults with a high repair rate and low hardware overhead. The proposed architecture divides the TSVs into several groups and connects the TSVs of each group using a 2:1 multiplexer chain. Simulation results show that the proposed architecture exhibits a repair rate of 98.52% for uniformly distributed faults and 69.86% for highly clustered faults. These repair rates are higher than those of other TSV redundancy architectures and the difference in the repair rate becomes even greater if the faults are more clustered. Moreover, the approach yields a 58.55% reduced area as compared to that of the router-based redundancy architecture, which also targets the repair of clustered faults.

Recently, three-dimensional integrated circuit (3-D IC) design has attracted much attention, and the reliability of these systems has become increasingly important. In this paper, a new repairable and reliable through-silicon via (TSV) set structure is proposed. This proposed TSV set structure can be applied to the previous TSV repair structures which require TSV redundancies, and detects a defect or error reutilizing residual TSV redundancies for high reliability of 3-D ICs. Both online test and soft error detection/analysis are supported by the proposed approach. Furthermore, a redundancy-sharing structure is introduced to guarantee a balanced detection rate among TSV sets and a reasonable full detection rate. The experimental results prove that the new approach guarantees high redundancy utilization efficiency and reliability of TSV. Also, they show that defect or error detection is achieved by the proposed TSV set structure.

A chain-based coupling delay estimation method for through-silicon-vias (TSVs) in 3-D integrated circuits is proposed. Existing works target the worst case scenarios and this leads to inaccurate TSV coupling delay estimations, as the worst case may not occur during normal operation. The proposed method calculates the TSV coupling delay using simulation-based switching data. In addition, our TSV chain method allows us to capture the effects of nonneighboring TSVs accurately. Our simulations show that the error introduced by our method without using HSPICE is less than 10 ps even in TSV-crowded regions.

In this paper, a receiver algorithm for an 8times8 MIMO system is considered for Giga-bps data transmission, in which the decoding complexity and latency are crucial factors for implementation of MIMO system with large number of transmit and receive antennae. To reduce computational complexity and the decoding latency, a 3-stage receiver algorithm is proposed. The MIMO receiver consists of multi-dimensional detection, partial interference cancellation and the weighted zero-forcing equalization, where the transmit antennae are divided into two group. The first group is encoded by a lower rate code and multi-dimensional search algorithm is used for demodulation and decoding, while the second group is encoded by higher rate code and weighted zero-forcing equalization is used. Once the first group is decoded successfully, they are cancelled out from the received vector for the decoding of the second group. The complexity and the error rate performance are investigated and compared with a well-known sphere decoding algorithm.

In this paper, we propose a design methodology of low-density parity check (LDPC) code for very high speed transmission. To support various code rates with reasonable hardware and, possibly, the type-II hybrid automatic repeat request (HARQ), a row-splitting/combining method is employed in conjunction with shortening. In row-splitting approach, a parity check matrix of a high rate mother LDPC code, saying rate 5/6, is designed first and then successively row-split the mother matrix to obtain lower rate codes. Shortening provides us another degree of freedom for rate and frame length flexibility for concatenation with MIMO system. The code performance is investigated in terms of frame error rate and compared with those of the LDPC code proposed in IEEE 802.16e standard.

Previously, there has been no report on implementation effort to integrate LDPC encoder and decoder into a single hardware. In this paper, we propose a simple yet low complex systematic LDPC encoding method for class of quasi-cyclic low-density parity-check (QC-LDPC) codes to let LDPC encoder acquire an interchangeable structure, exploited in the decoder. With the proposed encoding scheme, implementation of the proposed encoder becomes much more hardware efficient than having a separate hardware due to LDPC encoder and decoder resource sharing. Moreover, the overall computational complexity of the proposed encoding scheme is lower than the well-known Richardson's efficient encoding scheme (A.T.J. Richardson and R.L. Urbanke, 2001).

In this paper, we propose a simple yet low complex systematic LDPC encoding method for class of quasi-cyclic low-density parity-check (QC-LDPC) codes which have an efficient encoding/decoding algorithm due to the simple structure of their parity-check matrices. The proposed encoding method is applicable to parity-check matrices having dual-diagonal parity structure with single column of weight 3. Unlike finding a direct solution for parity bits in schemes (Richardson and Urbanke, 2001 and Classon and Blankeship, 2004), the proposed scheme first generates arbitrary parity bits. Then, given the parity bits for the first sub-block and exploiting the dual-diagonal structure, all parity bits are found through correction. With slight modification of parity-check matrix H, proposed LDPC encoding scheme is directly applicable to matrices defined in IEEE physical layer standards with almost negligible performance loss. Moreover, the overall computational complexity involving encoding process is lower than well-known Richardson's efficient encoding scheme (Richardson and Urbanke, 2001).

In this paper, we propose an efficient low complexity MIMO detection method for double space-frequency transmit diversity (D-SFTD) based coded OFDM system. The proposed MIMO detector involves three-step filtering process to efficiently de-correlate spatially-multiplexed and space-frequency-coded signals without direct matrix inversion process. As the proposed MIMO detector takes advantage of frequency selectivity, not a favorable channel condition for SFBC system, performance degradation caused by low correlation between two consecutive subcarriers is compensated by assigning weighting factor per subcarrier. From computer simulation results, our scheme in D-SFTD outperforms previously proposed suboptimal MIMO detection methods such as iterative interference cancellation based V-BLAST.

We consider the crosstalk cancellation problem when the transmit and receive signal spectrum are partially overlapped with each other in the frequency domain. In this case, the use of conventional crosstalk cancellers may not be practical due to the computational complexity. When the overlapped bandwidth of the crosstalk signal is less than the bandwidth of the transmit signal, the crosstalk cancellation can be realized efficiently by processing in the baseband. The use of interpolation and decimation processing in the baseband makes it possible to realize the crosstalk canceller with low computational complexity. The proposed scheme can provide crosstalk cancellation performance comparable to the conventional one, while requiring the computational complexity less than one half the conventional one

Digital subscriber lines (DSL) technology provides a transport of high-bit-rate digital information over the public telephone lines. Recently, a new technique has been proposed to increase the overall data rate by coordinating all the wires in the same DSL cable. However, this coordination method cannot be applied when the cable lines are used for different types of xDSL services. This paper proposes a dimensional decision-feedback equalizer (M-D DFE) and precoding method that can simultaneously coordinate the lines in the time and user domain. A modified decision-feedback substitution is proposed by applying a generalized DFE (G-DFE) scheme into the two dimensional domain to increase the cable capacity. The performance of the proposed scheme is verified by computer simulation.

For full-duplex high-speed data transmission over the two-wire line using the same frequency band, it is required to sufficiently suppress the echo. The use of a conventional adaptation method may take a long time to train the echo canceler. Fast training can be achieved by initializing the coefficients of the echo canceler with an estimate of the impulse response of the echo path. We propose a method for fast initialization of the echo canceler by using a circular convolution technique. The proposed method enables the use of real-valued training signals instead of complex-valued ones, resulting in significant reduction of the initialization time as well as the implementation complexity. Finally, the performance of the proposed method is analyzed and verified by computer simulation.