Energy Management System in Smart Buildings are commonly used to provide management solutions to optimize the performance about energy activities and in particular electrical energy. To be functional, they must be able to retrieve data and exploit them. In a Smart Building, data are usually provided by a Building Management System. The latter retrieves data from different sensors and formats them for the Energy Management System, so that it is decoupled from the technological aspect. The finer is the granularity of the data, the greater are the number of available management possibilities. Nevertheless, only for the consumption of various electrical appliances, installing measuring equipment on each of them can quickly become very complicated and annihilate any performance by an inappropriate installation and a costly overhead. The paper presents an innovative technique based on a knowledge of the electrical loads enabling to generate the load profile (power vs time) at very low power with dedicated electronics.

Non-Intrusive Appliance Load Monitoring can greatly benefit the Smart Buildings for energy awareness, while reducing cost and avoiding intrusive technology. This paper presents a generic algorithm for extracting the main power states of electrical appliances. The method is based on iterative K-mean clustering that is applied on historical plug-level active power data. The resulting multi-state load profile identification module is then integrated within an existing Building Management System for outlet-level energy disaggregation. Factorial Hidden Markov Modelling models the plugged appliances for low-frequency power disaggregation purposes, and incorporates the extracted set of appliances states. The solution was validated using the ECO dataset and NILM-Eval toolbox, allowing a comparison with standard binary ON/OFF modelling. It showed that the multi-state modelling significantly reduces the RMS error of the inferred power signals, yet at the expense of a higher computing time. Moreover, given a small set of appliances, the total inferred energy may be evaluated more precisely, leading to an enhancement of the quality of user energy feedback.

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic network is derived from the mesh generated through the existing mixed-signal design flow. The induced substrate model is included in circuit simulators such as SPICE to predict the effects of substrate couplings during the design phase. Furthermore, this analysis enables optimization of layout with minimal parasitic effects. By linking the substrate model to the active components, the couplings between the integrated circuit with the substrate parasitic currents can be analyzed during circuit simulations. Simulations and measurements on an high voltage driver reveal consistent results and therefore confirm the validity of the method. Therefore, the approach developed herein is effective to predict parasitic couplings due the injection of minority carriers.

In smart power IC technology, low and high voltage circuits are integrated on the same substrate. The commutation of the high voltage circuits can induce substrate parasitic currents which can severely disturb the operation of the low voltage circuits. The parasitic currents due to minority carriers in the high voltage technology can be significantly high. However, the minority carrier propagation into the substrate is not considered in most of existing circuit simulators. In this paper, a novel computer-aided design tool for substrate parasitic extraction is proposed. A simple circuit with an injecting and a collecting N-wells over a P-substrate is studied. With the distance between the wells varying, the lateral bipolar effect is illustrated. The spectre simulation results of extracted substrate equivalent circuit are compared to a TCAD simulation results. The comparison shows an acceptable relevant error. However, the simulation time was reduced by approximately 1400 times with respect to the TCAD.

This paper presents a fully integrated solar energy harvester for ultra-low power autonomous microsystems. This area- and power-efficient circuit harvests solar energy from a micro-power photovoltaic module to charge a rechargeable NiMH microbattery. As the harvested solar energy varies considerably in different lighting condition, the proposed circuit scales the power consumption and performance of the target microsystem, according to the harvested solar energy. Battery voltage is measured when battery is discharged by a high discharge current, to estimate harvested solar energy. Operating frequency and supply voltage of digital circuits and bias currents of analog circuits are reconfigured dynamically, based on measured battery voltage to optimize power-performance of the microsystem. This circuit occupies a core area of only 0.2mm2in a 0.18μm CMOS process and features a low power consumption of 390nW operating at its highest clock frequency.

This paper presents an integrated Hall sensor microsystem with continuous gain calibration and a current-mode back-end. The integrated system includes a Hall sensor with internal biasing, a fully differential front-end, a preamplifier chain, a voltage-to-current converter and internal voltage and current references. The main feature of this microsystem is full integration, including the references, which guarantee the gain stability. The whole microsystem is integrated in a 0.35µm CMOS technology. It occupies an area of 11.55mm2.

In this paper, a modeling methodology able to create an equivalent schematic of an High-Voltage integrated circuit is developed. The equivalent schematic is based on enhanced model of diodes and resistances, accounting for minority and majority carrier propagation at their boundary. In this work, the methodology to interconnect these elements in order to be able to model multi-dimensional current path is developed and applied to an industrial H-Bridge architecture. The coupled parasitic currents obtained with the equivalent schematic are compared against measurements and confirm that the model is accurate and can be used to estimate substrate parasitic signals.

This paper further examines the use of mixed-signal circuits for power system emulation. It has already been proven that analog emulation overcomes the speed limits of numerical simulators by means of a simple fixed-topology prototype. In order to enhance the modularity and the size of the emulated power system a dedicated platform based on a field programmable power network system (FPPNS) has been developed. This platform contains an application specific integrated circuit as main building block. Details on the designed hardware are given in this paper. Furthermore the emulator is validated comparing its emulation results with numerical reference simulations. The promising results of this platform show that the design of a fully integrated solution containing an array of 100 atoms can be started.

If an analog-to-digital converter (ADC) is used within a ΣΔ converter such that the loop filter is mixed signal, then the ADC does not need to have the full resolution of the ΣΔ converter, and its input values will not be uniformly distributed over the input range. In this paper, we argue that the best input distribution to use as a general model is the maximum-entropy distribution (for location parameters: the Gaussian distribution). We then describe an externally linear ADC with non-linearly spaced decision boundaries implemented in 0.6μm CMOS and show measurement results of a 19-bit dynamic range ΣΔ accelerometer loop inside which the ADC reaches more than the required 7-bit performance with only 26decision levels.

Autonomous transceivers working in the ISM' UHF hands should meet both requirements of a long battery lifetime and a small overall volume, thus implying to cut the receiving power consumption down to less than 1 mW.Ultimately, this goal will only be reached by using original topologies and lowering the supply voltage down to single battery cell operation.A RF front-end and a power-amplifier (PA) designed for the 433 MHz European ISM band are presented.Both RF building blocks have been integrated in a standard 0.5 urn digital CMOS process with 0.65 V threshold voltages.The front-end includes an LNA and a downconverter mixer.It achieves a total double sideband (DSB) noise figure of 9 dB, with a dynamic range of 8.5 dB for a 60 kHz bandwidth, while dissipating only 250 uW at 1.2 V supply voltage.The PA includes two fully integrated Class A stages together with an output Class C amplifier.It achieves a +4 dBm output power with a 15 % overall efficiency under 1.2 V supply voltage.