The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in order to efficiently reuse simulation stimuli and response for the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our ProTest system closes the gap between the simulation and the test environment with a low cast and easy to use computer-aided-test environment.

An arithmetic approach to extract the potential physical defects from the specific circuit layout of an integrated circuit is proposed. The defects subsequently are transformed into circuit faults and weighted according to their likelihood of occurrence. Based on these open and short faults extracted from CMOS layouts, an automatic test pattern generator is implemented. The test synthesis of some combinational CMOS benchmark circuits illustrates the superiority of the CMOS fault models and their application to test pattern generation as compared with the classical stuck-at fault models.>

A methodology relating physical defects to the circuit-level faulty behavior caused by these defects and a fast algebraic implementation to provide a realistic fault list are proposed. In conjunction with the obtained statistical data on the likelihood of each fault and the knowledge of its best observable electrical manifestation, a solid basis for an effective and powerful test pattern generation is provided. To achieve an accurate modeling of bridging faults, a novel fault model, the large-scope short, is developed and implemented. In contrast to other fault analysis procedures which use time-consuming simulation methods to generate or induce physical defects, the proposed Fantestic methodology is very fast in extracting defects and converting them to a ranked fault list. The analysis of some sample CMOS circuits illustrates the effect of different physical defects on circuit-level faults.>