Interposer-based 2.5-D integrated circuits (ICs) are seen today as a first step toward the eventual industry adoption of 3-D ICs based on through-silicon vias (TSVs). The TSVs and the redistribution layer (RDL) in the silicon interposer, and micro-bumps in the assembled chip must be adequately tested for product qualification. We present an efficient interconnect-test solution that targets TSVs, RDL wires, and micro-bumps for shorts, opens, and delay faults. The proposed test technique is fully compatible with the IEEE 1149.1 Standard. To reduce test cost, we also present a test-path design and scheduling technique that minimizes a composite cost function based on test time and the design-for-test overhead in terms of additional TSVs and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a single test path. We present simulation results to demonstrate the effectiveness of fault detection, and synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 Standard. We also present test-path design and test-scheduling results to highlight the effectiveness of the optimization technique.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. We present an efficient built-in self-test (BIST) architecture for targeting defects in dies and in the interposer interconnects. The proposed BIST architecture can also be used for fault diagnosis during interconnect testing. To reduce the overall test cost, we describe a test scheduling and optimization technique under power constraints. We present simulation results to validate the BIST architecture and demonstrate fault detection, synthesis results to evaluate the area overhead of the proposed BIST architecture, and test scheduling results to highlight the effectiveness of the optimization approach.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a precursor to 3D ICs based on through-silicon vias (TSVs). All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. We present an efficient built-in self-test (BIST) architecture for targeting defects in dies and in the interposer interconnects. The proposed BIST architecture can also be used for fault diagnosis during interconnect testing. We present simulation results to validate the BIST architecture and demonstrate fault detection, synthesis results to evaluate the area overhead of the proposed BIST architecture, and fault coverage results to highlight the effectiveness of the proposed technique.

Interposer-based 2.5D integrated circuits (ICs) are seen today as a first step towards the eventual industry adoption of 3D ICs based on through-silicon vias (TSVs). The TSVs and the redistribution layer (RDL) in the silicon interposer, and micro-bumps in the assembled chip must be adequately tested for product qualification. We present an efficient interconnect-test solution that targets TSVs, RDL wires, and micro-bumps for shorts, opens, and delay faults. The proposed test technique is fully compatible with the IEEE 1149.1 Standard. To reduce test cost, we also present a test-path design and scheduling technique that minimizes a composite cost function based on test time and the design-for-test overhead in terms of additional TSVs and micro-bumps needed for test access. We present simulation results to demonstrate the effectiveness fault detection, and synthesis results to evaluate the hardware cost per die relative to 1149.1. We also present test-path design and test-scheduling results to highlight the effectiveness of the optimization technique.

While the IEEE P1500 standards working group is on the verge of recommending a standard test interface for non-mergeable cores, a need was felt to adopt a standard methodology to achieve easy test interoperability for non-merged core (RTL, gate level) integration. A task force was formed under the P1500 working group investigating this issue and came up with a recommendation. DFT Disclosure Document (DDD) was the outcome of this exercise. The DDD, targeted to be an IEEE standard recommended practice document, aims at capturing the DFT related experience the core provider would like to share with the integrator to facilitate easy test integration. This paper presents the objective and structure of this document along with some use models from participating companies as well as an example.

This paper introduces a novel scheme for testing register-transfer level (RTL) controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) graph. This TCDF is used to derive a set of symbolic justification and propagation paths (known as the test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDF's, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. The test environment of an operation (variable) guarantees the existence of a path from the primary inputs of the circuit to the inputs of the module (register) to which the operation (variable) is mapped, and a path from the output of the module (register) to a primary output of the circuit. Since the search for a test environment is done symbolically, it is very fast and needs to be done only once for each module or register,in the circuit. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can he analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Unlike many RTL BIST schemes, an increase in the data path bit-width does not adversely impact the complexity of our testability analysis scheme since the analysis is symbolic. Every module in the module library is made random-pattern testable, whenever possible, using gate-level testability insertion techniques. This is a one-time cost. Finally, a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed on the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme. The average area overhead of the scheme is 6.9% which is much lower than many existing logic-level BIST schemes. The average delay overhead is only 2.5%. The test application time to achieve the high fault coverage for the whole circuit is also quite low.

In this paper, we explore two techniques, under the existing scan-based built-in self-test (BIST) architectures, for improving the test quality with practically no additional overhead. The proposed techniques are an almost-full-scan BIST strategy and a general scan-based BIST test application scheme. We first demonstrate that under the scan-based BIST architecture, full scan may not result in the highest fault coverage (FC) and unscanning a small number of scan flip-flops may increase the BIST FC. We then present an algorithm for identifying those not-to-be-scanned flip-flops. We further show that the proposed general scan-based BIST test application scheme could also result in higher BIST FC and only requires a minor modification to the BIST controller. Experiments have been conducted using an industrial tool, psb2, on benchmark circuits to illustrate the effectiveness of the proposed techniques and algorithms. The results have demonstrated that both techniques are able to maximize the FC and reduce the test application time without additional test hardware compared to the conventional scan-based BIST architectures.

In this paper, we propose a general test application scheme for existing scan-based BIST architectures.The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT).The proposed test scheme divides the entire test process into multiple test sessions.A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults.We present a procedure to find the optimal number of capture cycles following each scan sequence for every fault.Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.We conduct experiments on ISCAS89 benchmark circuits to demonstrate the effectiveness of our approach.

This paper introduces a novel scheme for testing register-transfer level controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) which consists of operations mapped to modules in the circuit and variables mapped to registers. This TCDF is used to derive a set of symbolic justification and propagation paths (known as test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDFs, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can be analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Every module in the module library is made random-pattern testable, whenever possible, using gate-level testability insertion techniques. Finally, a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed on the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme in a small number of test cycles at an average area (delay) overhead of only 6.4% (2.5%).

Path-delay faults represent a fault model that is commonly used to detect timing anomalies in a circuit. Unlike stuck-at faults which can be detected using ATE at lower speed, test for path-delay faults require ATEs that can run at the clock frequency of the circuit under-test. However, with ever-increasing circuit-speed and complexity, ATEs are unable to keep up with this growing trend. Moreover running deterministic tests for timing related defects on expensive ATEs for high-speed circuits consume enormous test application time. In this paper, we propose a BIST methodology for path-delay faults in sequential circuits. The proposed technique is based on an existing BIST architecture for stuck-at faults such that timing faults in a circuit can also be addressed with minimum additional effort. A new clocking scheme along with a novel technique for placing observation points that increases the fault coverage for path-delay faults is presented. Experimental results on some benchmark circuits show high path-delay fault coverage for sequential circuits.

This paper illustrates that for existing scan-based Built-In Self-Test (BIST) architectures under the pseudo-random testing scheme, scanning all flip-flops may not be the best strategy for achieving high fault coverage with a practical limit on test length. In general, for scan-based BIST, not scanning flip-flops with relatively high pseudo-random observabilities through the primary outputs may indeed improve the fault coverage as well as the test application time. We illustrate the issues and present a flip-flop selection strategy for scan-based BIST to maximize the fault coverage and reduce the test application time. Experiments have been conducted based on an industrial tool psb2 for several benchmark circuits. The results show that the almost-full-scan circuits based on our flip-flop selection strategy can achieve higher fault coverages and significantly shorter test application time as compared with the full-scan circuits.

We propose a test point selection algorithm for scan-based built-in self-test (BIST). Under a pseudorandom BIST scheme, the objectives are (1) achieving a high random pattern fault coverage, (2) reducing the computational complexity, and (3) minimizing the performance as well as the area overheads due to the insertion of test points. The proposed algorithm uses a hybrid approach to accurately estimate the profit of the global random testability of a test point candidate. The timing information is fully integrated into the algorithm to access the performance impact of a test point. In addition, a symbolic procedure is proposed to compute testability measures more efficiently for circuits with feedbacks so that the test point selection algorithm can be applied to partial-scan circuits. The experimental results show the proposed algorithm achieves higher fault coverages than previous approaches,with a significant reduction of computational complexity. By taking timing information into consideration, the performance degradation can he minimized with possibly more test points.

We propose a new algorithm for test point selection for scan-based BIST. The new algorithm combines the advantages of both explicit-testability-calculation and gradient techniques. The test point selection is guided bya cost function which is partially based on explicit testability recalculation and partially on gradients. With an event-driven mechanism, it can quickly identify a set of nodes whose testability need to be recalculated due to a test point, and then use gradients to estimate the impact of the rest of the circuit. In addition, by incorporating timing information into the cost function, timing penalty caused by test points can be easily avoided. We present the results to illustrate that high fault coverages for both area- and timing-driven test point insertions can be obtained with a small number of test points. The results also indicate a signi#cant reduction of computational complexity while the qualities are similar to the explicitly-testability-calculation method. 1 I...

Partial-scan based built-in self-test (PSBIST) is a versatile design for testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. While PSBIST provides all the benefits of BIST, it incurs less area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage.>

One of the techniques used to tackle the increasing complexity of testing VLSI circuits is to incorporate built-in self-test (BIST) structures. However, incorporation of such BIST structures calls for increased area overhead due to additional logic gates and interconnections. It is very important to keep this area overhead to a minimum. The authors present a simple graph model of the area overhead minimization problem, for circuits into which BIST modifications are to be incorporated. Although the graph model does not account for a mixed type of BIST structure usage, it can be extended to include them at the cost of increased complexity.>