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Thomas Müller 0012

dblp:38/6310-12 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 56% Parallel and multicore computing · 44%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
instruction scheduling		 0.011993
Employing finite automata for resource scheduling · MICRO 1993
Processor architecture and microarchitecture
instruction scheduling		 0.011993
Employing finite automata for resource scheduling · MICRO 1993
Parallel and multicore computing › parallel scheduling
static scheduling		 0.011993
Employing finite automata for resource scheduling · MICRO 1993
Processor architecture and microarchitecture
superscalar processor		 0.011993
Employing finite automata for resource scheduling · MICRO 1993

Methods — techniques the papers use, named apart from their topics

reservation tables · 0.0finite automata · 0.0
YearPublicationVenuePosition
1993 Employing finite automata for resource scheduling
abstract
The Motorola 88110 is an advanced superscalar design. The processor can issue up to two instructions per cycle among ten functional units, and it includes sophisticated load-store, speculative execution, exception recovery, and branch target buffer facilities. This paper examines several computationally inexpensive instruction scheduling strategies for a post-processor code optimizer for the 88110, including basic block scheduling using reservation tables for writeback buses as well as functional units, delayed branch removal, loop alignment, and special loop entry scheduling. For a set of 32 loop-intensive benchmarks, a combination of delayed branch removal and loop alignment yields the best code improvement.>
Thomas Müller 0012
 MICRO1