Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Michael Kantrowitz

dblp:38/6542 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
coverage analysis
0.011996
I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor · DAC 1996
Electronic design automation
hardware verification and test
0.011996
I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor · DAC 1996
Electronic design automation › hardware verification and test › functional verification
simulation-based verification
0.011996
I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor · DAC 1996
Processor architecture and microarchitecture
microprocessor design
0.011996
I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor · DAC 1996

Methods — techniques the papers use, named apart from their topics

pseudorandom exercisers · 0.0implementation-directed test generation · 0.0
YearPublicationVenuePosition
1996 I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor
abstract
Digital's Alpha-based DECchip 21164 processor was verified extensively prior to fabrication of silicon.This simulation-based verification effort used implementation-directed, pseudorandom exercisers which were supplemented with implementationspecific, hand-generated tests.Special emphasis was placed on the tasks of checking for correct operation and functional coverage analysis.Coverage analysis shows where testing is incomplete, under the assumption that untested logic often contains bugs.Correctness checkers are various mechanisms (both during and after simulation) that monitor a test to determine if it was successful.This paper details the coverage analysis and correctness checking techniques that were used.We show how our methodology and its implementation was successful, and we discuss the reasons why this methodology allowed several minor bugs to escape detection until the first prototype systems were available.These bugs were corrected before any chips were shipped to customers.
Michael Kantrowitz, Lisa M. Noack
DAC1