This paper introduces a Reinforcement Learning (RL)-based framework for optimizing early-exit configurations in Deep Neural Networks (DNNs). By integrating RL with BranchyNet-inspired architectures, the framework dynamically determines optimal early exit placements and confidence thresholds, balancing inference time, energy consumption, and accuracy. Key contributions include an early-exit DNN architecture search, an RL-driven threshold optimization process during training, and a design-space exploration open-source framework. Experiments on models such as ResNet-18, VGG-16, and AlexNet, using benchmarks like CIFAR-10 and MNIST, reveal significant reductions in inference time (up to 69.7x) and power consumption while keeping accuracy drop within 1-2%. This work demonstrates that dynamic early-exit strategies can enhance DNN efficiency while maintaining performance, paving the way for resource-constrained applications.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Semiconductor supply chain vulnerability presents a significant obstacle to creating reliable systems. At various phases of the Integrated Circuit (IC) design life-cycle, malicious modifications, known as Hardware Trojans (HTs), can be introduced. Logic testing, a widely recognized approach for Automatic test pattern Generation (ATPG) in HT detection, encounters substantial challenges due to the vast complexity of the search space, making it impractical and leading to inadequate trigger coverage. This paper proposes a Particle Swarm Optimization (PSO) based method that leverages information on effective inputs to facilitate the detection of conditionally triggered ultra-small HTs. An evaluation of the technique on ISCAS-85 benchmarks reveals substantial improvements in trigger coverage and a notable reduction in runtime compared to state-of-the-art methods.

Dynamic Deep Neural Networks (D2NNs) with early exits have emerged as an effective architecture for reducing computational overhead and inference latency. While fault tolerance in their static counterparts has been extensively studied, the dynamic models remain largely unexplored for enhanced reliability. This paper addresses that gap by developing Bayesian optimization algorithms to determine optimal early-exit confidence thresholds for enhanced fault resilience in dynamic DNNs. We present a reliability assessment of BranchyNet models compared to their static counterparts across three state-of-the-art architectures, introducing random bit flips (up to 0.01% of total model parameters) across 11 logarithmically increasing Bit Error Rates (BERs). The study analyzes fixed and adaptive thresholds that dynamically adjust considering the estimated fault rates. The results demonstrate that BranchyNet models exhibit greater fault resilience, preserving accuracy even at BER levels up to 2× higher than those tolerated by static models, with adaptive thresholds providing the strongest resilience. By combining exit threshold tuning with multiple inference pathways, early-exit DNNs offer a practical means to mitigate radiation-induced soft errors in hardware deployments.

This paper presents FORTUNE, a hardware-agnostic fault tolerance technique for DNNs that leverages quantization to enhance reliability without significant performance overhead. Unlike conventional methods like Triple Modular Redundancy (TMR), which are computationally expensive, the proposed approach uses memory savings from quantization to protect the critical Most Significant Bit, improving fault tolerance in Deep Neural Networks (DNNs). Memory utilization has been reduced by 37.5% across all networks, with vulnerability in AlexNet reduced by 56% compared to the 8-bit version and 84% compared to the unprotected 3-bit version. These improvements come with only a minor increase in execution time of less than 3%. Using AlexNet as an example demonstrates how our approach effectively enhances memory utilization and resilience while causing only a minimal increase in execution time.

Systolic array has emerged as a prominent archi-tecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essen-tial for deploying DNNs across diverse applications. However, when used in safety-critical applications, reliability assessment is mandatory to guarantee the correct behavior of DNN accelerators. While fault injection stands out as a well-established practical and robust method for reliability assessment, it is still a very time-consuming process. This paper addresses the time efficiency issue by introducing a novel hierarchical software-based hardware-aware fault injection strategy tailored for systolic array-based DNN accelerators. The uniform Recurrent Equations system is used for software modeling of the systolic-array core of the DNN accelerators. The approach demonstrates a reduction of the fault injection time up to 3 × compared to the state-of-the-art hybrid (software/hardware) hardware-aware fault injection frameworks and more than 2000 × compared to RT-level fault injection frameworks - without compromising accuracy. Additionally, we propose and evaluate a new reliability metric through experimental assessment. The performance of the framework is studied on state-of-the-art DNN benchmarks.

Multiplication is the most resource-hungry operation in the neural network’s processing elements. In this paper, we propose an architecture of a novel adaptive fault-tolerant approximate multiplier tailored for ASIC-based DNN accelerators. AdAM employs an adaptive adder relying on an unconventional use of the leading one position value of the inputs for fault detection through the optimization of unutilized adder resources. The proposed architecture uses a lightweight fault mitigation technique that sets the detected faulty bits to zero. The hardware resource utilization and the DNN accelerator’s reliability metrics are used to compare the proposed solution against the triple modular redundancy (TMR) in multiplication, unprotected exact multiplication, and unprotected approximate multiplication. It is demonstrated that the proposed architecture enables a multiplication with a reliability level close to the multipliers protected by TMR utilizing 63.54% less area and having 39.06% lower power-delay product compared to the exact multiplier.

Convolutional Neural Networks (CNNs) have become integral in safety-critical applications, thus raising concerns about their fault tolerance. Conventional hardwaredependent fault tolerance methods, such as Triple Modular Redundancy (TMR), are computationally expensive, imposing a remarkable overhead on CNNs. Whereas fault tolerance techniques can be applied either at the hardware level or at the model levels, the latter provides more flexibility without sacrificing generality. This paper introduces a model-level hardening approach for CNNs by integrating error correction directly into the neural networks. The approach is hardwareagnostic and does not require any changes to the underlying accelerator device. Analyzing the vulnerability of parameters enables the duplication of selective filters/neurons so that their output channels are effectively corrected with an efficient and robust correction layer. The proposed method demonstrates fault resilience nearly equivalent to TMR-based correction but with significantly reduced overhead. Nevertheless, there exists an inherent overhead to the baseline CNNs. To tackle this issue, a cost-effective parameter vulnerability based pruning technique is proposed that outperforms the conventional pruning method, yielding smaller networks with a negligible accuracy loss. Remarkably, the hardened pruned CNNs perform up to $\mathbf{2 4 \%}$ faster than the hardened un-pruned ones.

Since Deep Neural Networks (DNNs) gracefully withstands approximation due to its inherent redundancy, Approximate Computing (AxC) can be applied to reduce power consumption and execution time. In the literature, several works adopted the AxC paradigm to DNNs in the form of quantization, precision reduction, pruning, and functional approximation. Despite the promising results demonstrated so far, most of the existing works have applied homogeneous AxC techniques, meaning that the same degree of approximation has been applied to the entire DNN. However, different DNN components (i.e., channels, filters, layers, neurons) have different resiliency levels. This paper presents a framework for applying heterogeneous AxC to DNN hardware accelerators. The framework is based on the identification of channel resilience and applying a tailored degree of approximation per channel. Preliminary results carried out on the LeNet-5 model show that by using the proposed framework it is possible to decrease resource utilization by 65.2% and power consumption by 53.4% at the cost of a marginal drop of accuracy from 98.87% to 98.03%.

Reliability assessment is mandatory to guarantee the correct behavior of Deep Neural Network (DNN) hardware accelerators in safety-critical applications. While fault injection stands out as a well-established, practical and robust method for reliability assessment, it is still a very time-consuming process. This paper contributes with three recipes for optimizing the efficiency of the reliability assessment: a) hybrid analytical and hierarchical FI-based reliability assessment for systolic-array-based DNN accelerators; b) mixing techniques for the reliability assessment of in-chip AI accelerators in GPUs; c) reliability assessment of DNN hardware accelerators through physical fault injection. The experimental results demonstrate the efficiency of the proposed methods applied to their target DNN HW accelerator platforms.

Nowadays, the extensive exploitation of Deep Neural Networks (DNNs) in safety-critical applications raises new reliability concerns. In practice, methods for fault injection by emulation in hardware are efficient and widely used to study the resilience of DNN architectures for mitigating reliability issues already at the early design stages. However, the state-of-the-art methods for fault injection by emulation incur a spectrum of time-, design-and control-complexity problems. To overcome these issues, a novel resiliency assessment method called APPRAISER is proposed that applies functional approximation for a non-conventional purpose and employs approximate computing errors for its interest. By adopting this concept in the resiliency assessment domain, APPRAISER provides thousands of times speed-up in the assessment process, while keeping high accuracy of the analysis. In this paper, APPRAISER is validated by comparing it with state-of-the-art approaches for fault injection by emulation in FPGA. By this, the feasibility of the idea is demonstrated, and a new perspective in resiliency evaluation for DNNs is opened.

Deep Neural Networks (DNNs) and their accelerators are being deployed ever more frequently in safety-critical applications leading to increasing reliability concerns. A traditional and accurate method for assessing DNNs’ reliability has been resorting to fault injection, which, however, suffers from prohibitive time complexity. While analytical and hybrid fault injection-/analytical-based methods have been proposed, they are either inaccurate or specific to particular accelerator architectures.In this work, we propose a novel accurate, fine-grain, metric-oriented, and accelerator-agnostic method called DeepVigor that provides vulnerability value ranges for DNN neurons’ outputs. An outcome of DeepVigor is an analytical model representing vulnerable and non-vulnerable ranges for each neuron that can be exploited to develop different techniques for improving DNNs’ reliability. Moreover, DeepVigor provides reliability assessment metrics based on vulnerability factors for bits, neurons, and layers using the vulnerability ranges.The proposed method is not only faster than fault injection but also provides extensive and accurate information about the reliability of DNNs, independent from the accelerator. The experimental evaluations in the paper indicate that the proposed vulnerability ranges are 99.9% to 100% accurate even when evaluated on previously unseen test data. Also, it is shown that the obtained vulnerability factors represent the criticality of bits, neurons, and layers proficiently. DeepVigor is implemented in the PyTorch framework and validated on complex DNN benchmarks.

The accelerated growth of computing systems' complexity makes comprehensive design verification challenging and time-consuming. In practice, hard-to-model complex environments are unfeasible to be simulated exhaustively within a reasonable time frame. Therefore, some corner-case conditions can be overlooked and design errors might escape to the final product. This means that it is imperative for the system to be able to detect and locate bugs to enable self-repair. This is particularly crucial during long-term remote missions in order to apply graceful degradation. This paper proposes a novel online design error localization methodology for microprocessors by immediate analysis of traced and buffered signals upon a failure detection event, using a pre-trained Neural Network (NN) and existing processor components, i.e. trace buffers and AI accelerators. An in-house Neural Architecture Search (NAS) framework is used to train a tailored Multi-Layer Perceptron (MLP) NN for error localization at the microprocessor module-level resolution. The proposed approach is validated by simulating a RISC-V implementation with different workload programs. It is demonstrated to be capable of localizing the microprocessor module of bug origin with 92.81% accuracy, on average.

Deep Learning, and in particular, Deep Neural Network (DNN) is nowadays widely used in many scenarios, including safety-critical applications such as autonomous driving. In this context, besides energy efficiency and performance, reliability plays a crucial role since a system failure can jeopardize human life. As with any other device, the reliability of hardware architectures running DNNs has to be evaluated, usually through costly fault injection campaigns. This paper explores approximation and fault resiliency of DNN accelerators. We propose to use approximate (AxC) arithmetic circuits to agilely emulate errors in hardware without performing fault injection on the DNN. To allow fast evaluation of AxC DNN, we developed an efficient GPU-based simulation framework. Further, we propose a fine-grain analysis of fault resiliency by examining fault propagation and masking in networks.

With deep submicron scaling, the occurrence of soft errors has become a major reliability challenge for electronic systems. This work proposes a Machine Learning-based Checker (MLC) to protect hard-core processors against radiation-induced soft errors. MLC is an independent hardware unit that implements an ML algorithm to detect soft errors in a processor. The work presented here selects input features from key processor signals for creating a dataset for training. The dataset trains an ML model offline for learning the correct behavior of the processor and detecting soft errors at run-time. The inference of this trained ML is implemented in the MLC hardware that runs along with the processor. Several ML models have been considered for the inference phase, and XGBoost implementation has shown to be the best in terms of hardware overhead and accuracy. The proposed scheme is applied to a RISC-V-like processor, called SAYAC, as a case study.

We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of fault-tolerant configurable circuits. The AND and OR gates consist of 8 transistors based on CNFET technology, while the proposed XOR gate benefits from both CNFET and low-power MGDI technologies in its transistor arrangement. To demonstrate the feasibility of our new logic gates, we used an AES S-box implementation as the use case. The extensive simulation results using HSPICE indicate that the case-study circuit using on proposed gates has superior speed and power consumption compared to other implementations with error-detection capability.

In this paper, a concept for generating tests for RISC processors is proposed relying solely on functional information such as the instruction set without any knowledge of the implementation details. For the first time, the effect-cause idea, instead of the traditional cause-effect fault driven approach, is applied for test generation. For implementing the effect-cause idea, a novel high-level constraint-based functional fault model is developed. This novelty made it possible to extend the classical Stuck-At Fault (SAF) model, applied so far in evaluating the quality of processor testing, not only to a large class of structural faults, such as conditional SAF, bridging faults, delay faults etc., but also to the functional faults similar to those covered by the March algorithm in memory testing. By experimental research it was demonstrated that the test quality of the proposed implementation-independent test generation method produces test sequences with comparable or better fault coverages for SAF and Transition Delay Faults (TDF) than known methods utilizing knowledge about the implementation details.

Recently, several research works have emphasized the problem of stealing the intellectual property of trained Machine Learning (ML) models from hardware neural network inference engines spotlighting Binarized Neural Networks (BNNs). The binary operations in BNNs can be executed bitwise, which notably saves storage memory, reduces the execution time and power and, therefore, makes them convenient for implementation in hardware. Unfortunately, these advantages may also enable a vulnerability to Differential Power Analysis (DPA) side-channel attacks, which, in turn, necessitates dedicated masking techniques to protect the models. Notably, the recent BNN hardware inference engines are being increasingly adopted for critical applications and demand, along with security, also high levels of in-filed reliability throughout their lifetime. The state-of-the-art power side-channel masking in BNNs implies glitch-resistant structures, such as Trichina AND gates and sequences of flip-flops, and may create soft-error reliability issues that are currently overlooked in the literature. This paper presents an analysis for the soft-error reliability jeopardy by the security countermeasures in hardware implementations of BNN inference engines. Our work reveals a steep increase (hundreds of times) of vulnerability to single-event effects, introduced by the state-of-the-art security enhancement techniques, and emphasizes the interdependency of the design’s reliability and security aspects.

The recent trends for nanoelectronic computing systems include machine-to-machine communication in the era of Internet-of-Things (IoT) and autonomous systems, complex safety-critical applications, extreme miniaturization of implementation technologies and intensive interaction with the physical world. These set tough requirements on mutually dependent extra-functional design aspects. The H2020 MSCAITN project RESCUE is focused on key challenges for reliability, security and quality, as well as related electronic design automation tools and methodologies. The objectives include both research advancements and cross-sectoral training of a new generation of interdisciplinary researchers. Notable interdisciplinary collaborative research results for the first halfperiod include novel approaches for test generation, soft-error and transient faults vulnerability analysis, cross-layer fault-tolerance and error-resilience, functional safety validation, reliability assessment and run-time management, HW security enhancement and initial implementation of these into holistic EDA tools.

Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always cause incorrect behavior, and therefore are easily detected by applying sequences of write and read operations. However, hard-to-detect (HTD) faults may not cause incorrect behavior, only parametric deviations. Detection of these faults is of major importance as they may lead to test escapes. This paper proposes a new design-for-testability (DFT) scheme for FinFET SRAMs to detect such faults by creating a mismatch in the sense amplifier (SA). This mismatch, combined with the defect in the cell, will incorrectly bias the SA and cause incorrect read outputs. Furthermore, post-silicon calibration schemes can be used to avoid over-testing or test escapes caused by process variation effects. Compared to the state of the art, this scheme introduces negligible overheads in area and test time while it significantly improves fault coverage and reduces the number of test escapes.

We propose a method for synthesis of Software-Based Self-Test (SBST) for testing RISC type of microprocessors without needing the knowledge of implementation details. The test covers a large class of faults and a special target is to detect Transition Delay Faults (TDF). To reduce the complexity, the processor is partitioned into Modules Under Test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, whereas for the control parts a novel functional control fault model was developed. The test is regular, represented in a compact form allowing easy unrolling during test execution. Experimental results demonstrate high Stuck-At Fault (SAF) and TDF coverage, despite the lack of knowledge of implementation details.

The advanced complex electronic systems increasingly demand safer and more secure hardware parts. Correspondingly, fault injection became a major verification milestone for both safety- and security-critical applications. However, fault injection campaigns for gate-level designs suffer from huge execution times. Therefore, designers need to apply early design evaluation techniques to reduce the execution time of fault injection campaigns. In this work, we propose a method to represent gate-level Single-Event Transient (SET) faults by multiple Single-Event Upset (SEU) faults at the Register-Transfer Level. Introduced approach is to identify true and false logic paths for each SET in the flip-flops' fan-in logic cones to obtain more accurate sets of flip-flops for multiple SEUs injections at RTL. Experimental results demonstrate the feasibility of the proposed method to successfully reduce the fault space and also its advantage with respect to state of the art. It was shown that the approach is able to reduce the fault space, and therefore the fault-injection effort, by up to tens to hundreds of times.

Physical Unclonable Functions (PUFs) are gaining attention in the cryptography community because of the ability to efficiently harness the intrinsic variability in the manufacturing process. However, this means that they are noisy devices and require error correction mechanisms, e.g., by employing Fuzzy Extractors (FEs). Recent works demonstrated that applying FEs for error correction may enable new opportunities to break the PUFs if no countermeasures are taken. In this paper, we address an attack model on FEs hardware implementations and provide a solution for early identification of the timing Side-Channel Attack (SCA) vulnerabilities which can be exploited by physical fault injection. The significance of this work stems from the fact that FEs are an essential building block in the implementations of PUF-enabled devices. The information leaked through the timing side-channel during the error correction process can reveal the FE input data and thereby can endanger revealing secrets. Therefore, it is very important to identify the potential leakages early in the process during RTL design. Experimental results based on RTL analysis of several Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon decoders for PUF-enabled devices with FEs demonstrate the feasibility of the proposed methodology.

The current demands for autonomous driving generated momentum for an increase in research in the different technologies required for these applications. Nonetheless, the limited access to representative designs and industrial methodologies poses a challenge to the research community. Considering this scenario, there is a high demand for an open-source solution that could support development of research targeting automotive applications. This paper presents the current status of AutoSoC, an automotive SoC benchmark suite that includes hardware and software elements and is entirely open-source. The objective is to provide researchers with an industrial-grade automotive SoC that includes all essential components, is fully customizable, and enables analysis of functional safety solutions and automotive SoC configurations. This paper describes the available configurations of the benchmark including an initial assessment for ASIL B to D configurations.

The identification of safe faults (i.e., faults which are guaranteed not to produce any failure) in an electronic system is a crucial step when analyzing its dependability and its test plan development. Unfortunately, safe fault identification is poorly supported by available EDA tools, and thus remains an open problem. The complexity growth of modern systems used in safety-critical applications further complicates their identification. In this article, we identify some classes of safe faults within an embedded system based on a pipelined processor. A new method for automating the safe fault identification is also proposed. The safe faults belonging to each class are identified resorting to Automatic Test Pattern Generation (ATPG) techniques. The proposed methodology is applied to a sample system built around the OpenRisc1200 open source processor.

A method is proposed for testability analysis of digital circuits focusing on calculating the probabilistic controllability measures in terms of signal probabilities, when random or pseudorandom patterns are applied to the circuit inputs. The tasks of calculating the probabilistic observability and testability measures are transformed into the task of calculating the controllability. The structure of the circuit is presented as a set of Structurally Synthesized BDDs (SSBDD), which allows controllability analysis with higher speed than carrying out calculations on the gate-level, retaining the possibilities of assessment of the controllability of all gate-level nodes represented by related SSBDD nodes. The proposed method is based on tracing true paths in SSBDDs. A general case is considered, where the circuit may include redundancies. It is shown that the known methods of calculating signal probabilities, which are not taking into account the redundancy in circuits, are not accurate. A method is proposed for proving the redundancy of faults, which is based on the same idea of SSBDD path tracing. Experimental results show higher accuracy and higher speed of SSBDD-based probability calculations, compared to gate-level calculation.

Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementation-independent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudo-exhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor.

This work proposes a fault injection methodology where Hardware Description Language (HDL) code slicing is exploited to prune fault injection locations, thus enabling more efficient campaigns for safety mechanisms evaluation. In particular, the dynamic HDL slicing technique provides for a highly collapsed critical fault list and allows avoiding injections at redundant locations or time-steps. Experimental results show that the proposed methodology integrated into commercial tool flow doubles the simulation speed when comparing to the state-of-the-art industrial-grade EDA tool flows.

The extreme complexity of digital systems enabled by nanometer-scale implementation technologies comes along with strengthened design requirements that are difficult to achieve with the conventional techniques. Over-designing beyond the minimal required guarantees may have negative impacts on the overall system's cost. In this paper we focus on the task of timing-critical logic paths identification in digital systems that has many applications in design and test field, like verifying the timing constraints of designs, estimating critical delays, Simulating path delay faults and reliability analysis such as ageing. The contribution is a new scalable simulation-based hierarchical search method for application-specific online-viable true critical paths identification in sequential circuits. The approach is motivated by the concept of mixed-critical systems, but it can be applied for any type of digital system. We propose to represent the circuits hierarchically at the level of higher level submodules using t e theory of Structurally Synthesized BDDs (SSBDD). The search space is limited by the application-specific context that enables accurate results even for complex sequential circuits. Experimental results demonstrate efficiency of the proposed approach, and considerable reduction of the length of critical paths if the application-specific constraints are taken into account.

A large number of crypto accelerators are being deployed with the widespread adoption of IoT. It is vitally important that these accelerators and other security hardware IPs are provably secure. Security is an extra functional requirement and hence many security verification tools are not mature. We propose an approach/flow - PASCAL - that works on RTL designs and discovers potential Timing Side Channel Attack (SCA) vulnerabilities in them. Based on information flow analysis, this is able to identify Timing Disparate Security Paths that could lead to information leakage. This flow also (automatically) eliminates the information leakage caused by the timing channel. The insertion of a lightweight Compensator Block as balancing or compliance FSM removes the timing channel with minimum modifications to the design with no impact on the clock cycle time or combinational delay of the critical path in the circuit.

The Negative Bias Temperature Instability (NBTI) phenomenon is one of the main reliability issues in today's nanoelectronic systems. It causes increase in threshold voltage of pMOS transistors, thus degrading signal propagation delay in logic paths between flip-flops. Recently, IEEE published a new standard IEEE 1687 for Reconfigurable Scan Networks (RSN) to facilitate access to embedded instrumentation within an integrated circuit. In the field, the RSN infrastructure is often exploited for fault-management in failure-sensitive critical parts of the system. Therefore, the severity level of a fault in the RSN itself is very high, thus, amplifying the impact of the reliability issues caused by the aforementioned effect. To the best of the authors' knowledge no approach has been proposed to investigate or address this issue so far. In this paper, we analyze the effect of NBTI-induced aging in RSNs from architectural and operational (functional) perspectives and present a novel technique to mitigate the degradation. The methodology is demonstrated on a a case-study example and the effectiveness of our approach is evaluated on a sub-set of ITC2016 benchmark RSN designs.

We propose a generic strategy for formalized synthesis of Software-Based Self-Test (SBST) for testing microprocessors with RISC architecture with the goal to achieve high gate-level fault coverage without knowing the gate-level implementation detail, and to have well-structured compact test, which can be easily unrolled on-line during test execution. The high-level model of the microprocessor is derived from the instruction set and from the architectural features introduced for increasing performance, like pipelining, forwarding, hazard handling, prediction, etc. A novel high-level functional control fault model is introduced, which has the capability of covering a broad class of gate-level faults. For the functional testing of data-path, bitwise pseudo-exhaustive test method is used. A novel method for measuring the high-level fault coverage is proposed. As an added value of the method, an efficient approach for identifying low-level redundant faults is described. Experimental results demonstrate high fault coverage achieved for MiniMIPS processor without using any information about gate-level implementation details.

Multi-Processor Systems-on-Chip (MPSoCs) have been a clear new trend in processor-based systems design. General purpose MPSoC designers have turned to the Network-on-Chip (NoC) interconnect model to surpass the limitations imposed by traditional bus- or crossbar-based interconnection. This technology is also a promising solution for safety-critical industries where, primarily due to power and weight constraints, there is an increasing need in embedded systems for implementing multiple functionalities upon a single shared computing platform. This paper proposes a QoSinNoC framework, which is based on a set of quality of service (QoS) aware NoC architectures along with the analysis methodology including selected relevant metrics that enable an efficient trade-off between guarantees and overheads in mixed-criticality application scenarios. QoSinNoC architectures overcome the notion of strictly divided regions by allowing non-critical communication pass through the critical region, providing they do not utilize common router resources. This work aims to facilitate the usage of NoC technology by safety-critical industries such as avionics.

Handling faults in computing systems is often expensive in terms of power, area and financial costs. In domains requiring high reliability in harsh environments, like the space domain, special highly reliable components are used, which may adversely impact the processing performance. In this paper, we propose the STROBES algorithm for fault handling in a multi-node embedded system which can be composed of standard commercial off-the-shelf components. In particular, it does not require underlying synchronization, but relies on embedded system's properties to derive bounds for communication and processing times. The algorithm can handle asynchronous behavior between the nodes up to user-defined bounds, in addition to a fault in the state or fail-stop failure of a single node. Theoretical analysis shows that this is sufficient for extended operating times. Experimental data show the efficient behavior of the STROBES algorithm for practical application with different state and time bounds.

Multi-processor system-on-chip (MPSoC) devices are a well known replacement of single-core devices. Some industries, like avionic, are particularly sensitive to the weight and power consumption. Such industries would really take advantage of reducing the number of computers by using MPSoCs. However, the usage of such devices in safety critical domain is currently more than limited. The main issue, which hinders the MPSoC usage in safety critical field, is the presence of on-chip resources shared by the cores. The interconnection itself is the most evident these shared resources. This aspect is an issue as it undermines the safety aspect of the system by providing non functional dependencies, especially from the timing point of view. The certification process is crucial in safety critical field and the system complexity makes the whole certification process harder and even unfeasible. The certification requires to prove that the system exhibits a precise set of guarantees to the safety-critical tasks. While the complexity was an issue for the well known bus-based MPSoCs, it becomes even more critical for the emerging network-on-chip (NoC) interconnection model. The QoSinNoC framework has been created to analyze a set of simple NoC architectures and the related techniques to enable their usage in the scope of mixed criticality. The main contribution of this work is an alternative routing algorithm which allows a better system utilization without any hardware modifications to the NoC architectures considered by QoSinNoC. Furthermore the framework has been upgraded with the power estimation feature which allows a better design space exploration.

This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.

The recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. The conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTI) induced aging, but also several others. In this paper, we propose a scalable simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like deciding the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. The paper demonstrates an efficient application of the proposed technique to gate-level NBTI-critical paths identification. The experimental results prove feasibility and scalability of the technique.

The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits implemented with current nanotechnology nodes. NBTI increases the threshold voltage of pMOS transistors: hence, it slows down signal propagation along logic paths between flip-flops. It may cause intermittent faults and, ultimately, permanent functional failures in processor circuits. In this paper, we study an NBTI mitigation approach in processor designs by rejuvenation of pMOS transistors along NBTI-critical paths. The method incorporates hierarchical fast, yet accurate modelling of NBTI-induced delays at transistor, gate and path levels for generation of rejuvenation Assembler programs using an Evolutionary Algorithm. These programs are applied further as an execution overhead to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay in processors. The experimental results demonstrate efficiency of evolutionary generation and significant reduction of NBTI-induced delays by the rejuvenation stimuli with an execution overhead of 0.1% or less. The proposed approach aims at extending the reliable lifetime of nanoelectronic processors.

CPS, that consist of a cyber part – a computing system – and a physical part – the system in the physical environment – as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment. This paper provides an overview of techniques discussed in the special session to tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements.

The rapid increase of embedded systems design complexity has resulted in emergence of design methodologies at higher levels of abstraction such as Electronic System Level (ESL) and Transaction Level Modeling (TLM) with SystemC language as the main instrument. In practice, system architects and system integrators often have access to a library of legacy Register Transfer Level (RTL) IP (Intellectual Property) cores or obtain new ones from IP design houses. To address architectural exploration, early prototyping and simulation performance, such RTL IP cores are manually recreated at more abstract levels, which implies significant and error-prone effort. The current paper proposes an approach for automated abstraction of the computational part of cycle-accurate RTL IP cores to untimed TLM using a novel concept of SystemC-based Loose Models (SCLM). SCLMs provide for an instrument to neglect design model parts irrelevant for particular manipulation step of the abstraction process, thus simplifying the abstraction flow. As a result, the computational complexity of the abstraction process is reduced, thus increasing the overall scalability. The proposed abstraction flow is demonstrated on a set of benchmark designs and the first experimental results prove feasibility of the proposed approach and also show considerable simulation speed-up.

Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced VTHp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.

SystemC has gained wide acceptance in the design of VLSI SoCs. At the same time there exists a large number of legacy IP cores described in VHDL whose reuse and integration into SystemC ecosystem is highly demanded. However, there is a lack of any standard approach in this regard. This paper proposes an open-source framework and methodology to convert RTL VHDL IP cores to cycle-accurate SystemC designs. The SystemC output is emphasized to be human-readable and providing for clear correspondence to the source VHDL code, thus allowing further manual code changes and debug. The described framework has been implemented based on an open-source zamiaCAD platform and has been successfully applied to translate various VHDL benchmark designs.

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It may increase the switching threshold voltage of pMOS transistors and as a result slow down signal propagation along the paths between flip-flops thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical paths in nanoscale logic that is based on analyzing combination in different degrees of the three parameters: delay-critical paths, gate input signal probability and the gate fan-out degree along the paths. Further the identified NBTI-critical path can be used e.g. for introduction of aging sensors circuitry, rejuvenation stimuli generation, etc. The proposed approach is demonstrated on an industrial ALU circuit design.

Verification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the occurrences of errors but on debugging, consisting of locating and correcting the errors. However, automated design-error debug, especially at the system-level, has received far less attention than error detection. Current paper presents an automated approach to correcting system-level designs. We propose dynamic-slicing and location-ranking-based method for accurately pinpointing the error locations combined with a dedicated set of mutation operators for automatically proposing corrections to the errors. In order to validate the approach, experiments on the Siemens benchmark set have been carried out. The experiments show that the proposed method is able to correct three times more errors compared to the state-of-the-art mutation-based correction methods while examining fewer mutants.

As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous size, and thus, to scale well. This paper presents an open-source framework zamiaCAD based on a scalable model that includes both, a comprehensive elaboration front-end for RTL design and design processing back-end flows. The persistence and scalability are guaranteed by a custom-designed and highly optimized object database. As an HDL-centric framework it follows the concept of non-intrusiveness. In this paper, we discuss in detail the concepts of design elaboration into the scalable design model and present an evaluation of the model for static analysis as one of the back-end applications. Experimental results on very large designs show that zamiaCAD compares favorable to other frameworks with respect to the scalability aspects.

The paper proposes a new hierarchical untestable stuck-at fault identification method for non-scan sequential circuits containing feedback loops. The method is based on deriving, minimizing and solving test path activation constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path activation constraints for a module under test. Then, the constraints are minimized and a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the tool is capable of quickly proving a large number of untestable faults obtaining high fault efficiency. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.

The paper introduces a novel constraint-based automated test pattern generator for Register-Transfer Level (RTL) designs. The tool combines test path constraint activation with a constraint solver. First, a deterministic algorithm that extracts constraints for activating test paths at RTL is applied. Subsequently, a constraint solving package ECLiPSe is used for assembling the tests. Experiments on ITC99 and HLSynth92/95 benchmarks show that the proposed deterministic method offers short run times. In particular, it provides increased fault coverage for hard-to-test designs with respect to earlier, semiformal, approaches.

Current paper proposes a new hierarchical approach to defect-oriented testing of CMOS circuits. The method is based on critical area extraction for identifying the possible shorted pairs of nets on the basis of the chip layout information, combined with logic-level test pattern generation. The novel contributions of the paper are a new bridging fault simulator and a test pattern generator, which are able to handle defects creating feedbacks into the circuit. As a preprocessing step, a combined stuck-at test set from two different test pattern generators implementing alternative strategies (pseudorandom and deterministic) were created. Nevertheless, many short defects were not covered by this extended stuck-at approach. Analyses carried out in this paper show that the stuck-at tests are not covering up to 4% of the shorts (both testable and untestable). The test coverage (fault efficiency) can be increased by the new generator by up to 0.4% in comparison to full stuck-at test. Layout analysis for a set of benchmarks has been performed. The experiments indicate how the number of bridging faults of non-zero probability is dependent on the circuit size.

The paper proposes a novel method for PSL language assertions simulation-based checking. The method uses a system representation model called High-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal properties expressed in PSL. Other contributions of the paper are methodology for direct conversion of PSL properties to HLDD and HLDD-based simulator modification for assertions checking support. Experimental results show the feasibility and efficiency of the proposed approach.

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper, we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.