We developed a method that predicts the required number of cores for executing threads in the near future on a many-core processor. It is designed for low power consumption without performance degradation. The evaluation result confirmed the proposed method is effective on a 32-cores processor.

Although SIMD instructions are effective for many digital signal processing applications, current compilers cannot take full advantage of SIMD instructions. One factor inhibiting SIMD code generation is control flow structure; the target scope of SIMD code generation is currently limited to single basic block or loop that consists of single basic block. SIMD instructions cannot be mapped typically across basic block boundaries even if basic blocks inside the control structure have enough parallelism. In this paper, a new compilation technique to generate SIMD code without modifying control flow structure is proposed. The data dependency between basic blocks is exploited to generate SIMD instructions. The packing cost is introduced for effective vectorization to maintain data dependency across basic block boundaries. Experimental results show that the new SIMD code generation technique reduced 67% of dynamic execution cycles of inter prediction in H.264 decoder.

In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the number of cores, and the application program is not affected by the actual number of cores. For the performance efficiency, we designed the threads so that they do not suspend and that they do not start their execution until the data necessary for them are available. We implemented our design using three modules: the dependency controller, which controls dependencies among threads, the thread pool, which manages the ready threads, and the thread dispatcher, which fetches threads from the pool and executes them on the core. Our design and implementation provide efficient thread scheduling with low overhead. Moreover, by hiding the actual number of cores, it realizes transparency. We confirmed the transparency and scalability of our scheme by applying it to the H.264 decoder program. With this scheme, modification of application program is not necessary even if the number of cores changes due to disparate requirements. This feature makes the developing time shorter and contributes to the reduction of the developing cost.

A new integrated system to design and generate a configurable embedded processor for multimedia applications has been developed. The system, "Media embedded Processor Integrator", provides a distinctive feature that generates development tools, such as compilers and simulators, not only for the configurable embedded processor but also for its template based extensible VLIW co-processor. This paper describes the architecture and the function of the "Media embedded Processor Integrator" especially focusing on how the system treats the VLIW co-processor extension. In order to determine an ISA for a 3-way VLIW co-processor for image recognition as an example, several different sets of ISA were evaluated and compared for the best performance using corresponding compilers and simulators, which were generated by the system. The system greatly contributed to reduce this entire ISA definition process.

A new test program generation tool, mVpGen, is developed for verifying pipeline design of microprocessors. The only inputs mVpGen requires are pipeline-behavior specifications; it automatically generates test cases at first from pipeline-behavior specifications and then automatically generates test programs corresponding to the test cases.

An algorithm independent layout compaction method for full chip layouts is proposed.The partitioning compaction method cuts up a large layout, compacts each block independently and then merges them to give the final compacted layout.A 16-bit CPU core (28.8Ktransistors) layout was compacted on a standard workstation using this method.Both the computer memory usage and processing time were reduced.Parallel processing is pcssible to further speed up the computation.

This paper describes a new datapath generator that generates high-density mask layouts equivalent to hand-crafted ones.