Computing modules in typical data center nodes or server racks consist of several multicore chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the destination chip over a wireline interconnect fabric. This multihop communication increases energy consumption while decreasing data bandwidth in a multichip system. Also, traditional I/O does not scale well with technology generations due to limitations of pitch. Moreover, intra-chip and inter-chip communication protocol within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. Here, we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.

This work presents a generalized analytical method to obtain the S and Z matrices for irregular shaped planar resonant structures commonly found in mixed signal circuits. The method is based on a segmentation technique that uses an interconnect matrix in conjunction with a cavity model where resonant modes are predicted accurately through closed form expressions. The analytical formulation is very versatile and can be applied to both digital and RF circuitry. Typical structures such as the L-shaped power plane, rectangular ring power plane and rectangular coil inductor are considered where the S and Z matrices have been compared with published literature and full wave solvers. In all cases, there is excellent agreement. A design methodology has been developed to shape the power planes so that no resonances occur within the frequency range of interest. In the case of inductors, a similar design methodology can be developed where a physical layout is obtained for a required inductance value.