Demo Data from EDBT 2026 / reviewers in the wild / expert
Jung-Chang Liu
dblp:38/7450
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › logic synthesis
boolean matching |
0.1 | 1 | 2009 | Simulation and SAT-based Boolean matching for large Boolean networks · DAC 2009 |
Electronic design automation
hardware verification and test |
0.1 | 1 | 2009 | Simulation and SAT-based Boolean matching for large Boolean networks · DAC 2009 |
Electronic design automation
logic synthesis |
0.0 | 1 | 2009 | Simulation and SAT-based Boolean matching for large Boolean networks · DAC 2009 |
Methods — techniques the papers use, named apart from their topics
unateness and symmetry analysis · 0.1simulation · 0.1boolean satisfiability · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | Simulation and SAT-based Boolean matching for large Boolean networksabstractBoolean matching is to check the equivalence of two target functions under input permutation and input/output phase assignment. This paper addresses the permutation independent (P-equivalent) Boolean matching problem. We will propose a matching algorithm seamlessly integrating Simulation and Boolean Satisfiability (S&S) techniques. Our proposed algorithm will first utilize functional properties like unateness and symmetry to reduce the searching space. In the followed simulation phase, three types of input vector generation and checking method will be used to match the inputs of two target functions. Experimental results on large benchmarking circuits demonstrate that our matching algorithm is indeed very effective and efficient to solve Boolean matching for large Boolean networks. Kuo-Hua Wang, Chung-Ming Chan, Jung-Chang Liu |
DAC | 3 |