Through silicon via (TSV), serving as the vertical signal path in 3-D integrated circuits (3D-ICs), must be tested prior to die bonding (pre-bond). Most conventional pre-bond TSV test methods are often limited in terms of leakage fault detection range, hybrid fault detection capability, and fault parameter diagnosability. To address these challenges, we propose a pre-bond TSV test method based on ring oscillator (RO) circuits using a variable discharge path, capable of detecting and diagnosing a wide range of TSV faults, including open, leakage, and hybrid open-leakage faults with high resolution. The entire DfT framework employs standard digital cells to construct all test structures, facilitating its application in diverse testing scenarios. The effectiveness of the proposed method is evaluated through HSPICE simulations. The simulation results demonstrate that, in the presence of PVT variation, the proposed method can effectively detect and diagnose open faults occurring within the first 96.7% tail section of TSV with a maximum diagnosing error of 3.71 fF. Additionally, it can accurately identify leakage faults exceeding 2.5 nS with a maximum diagnosing error of 13.5%.

Monolithic 3-D (M3D) integrated circuits (ICs) have the potential to achieve significantly higher device density compared with conventional ICs. The implementation of nanoscale interlayer vias (ILVs) in M3D plays a pivotal role in achieving enhanced transistor density and increased flexibility for circuit design. However, the high integration density and aggressive scaling of the interlayer dielectric make ILVs especially prone to defects. In this article, we propose a post-bond ILV test method for the detection and diagnosis of ILVs’ open faults, stuck-at faults (SAFs), and short faults in the fabrication process of M3D ICs. The proposed method is well-suited for post-bond ILV test, which can significantly save the cost and improve the yield. The HSPICE simulation results demonstrate that the proposed method can effectively detect and localize ILVs’ open, stuck-at 0, stuck-at 1, and short faults. Evaluation results for M3D benchmarks demonstrate the proposed method has a quite small power-performance–area (PPA) overhead and a relatively low test-time overhead.

During the manufacturing process of three-dimensional integrated circuits (3-D ICs), many defects may occur in through-silicon vias (TSVs). These defects affect the integrity of the signal passing through TSVs, therefore detecting these defects in the early production stage is crucial. This article proposed a built-in-self-test (BIST) method with a simple test structure and easily implemented fault detection process. Due to the fact that the defects in TSVs influence the charge/discharge speed of TSVs’ equivalent capacitance, a weak current source is designed as the central part of the proposed test structure, which can measure the TSVs’ charge/discharge speed and quantify it using digital values. The effectiveness and robustness of the proposed method is validated by HSPICE simulation. The minimum measurable fault, test time, and test circuit area are also assessed in this article. The simulation results show that the method this article proposed can detect weaker faults, compared with the traditional test methods.

In this paper, we propose a novel post-bond through-silicon via (TSV) test method for post-bond TSV manufacture test. The proposed method can measure the RGC parameters of TSVs using switched-capacitor circuits and calibration method and detect TSV leakage fault, open fault, high-resistance fault, and delay fault based on the measured RGC parameters. The test process has a high resolution and is robust. The fault-detection effectiveness is evaluated via HSPICE simulations. The results of the TSV capacitance measurement have a relative error within 1%, the TSV resistance measurement results have a relative error within 5%, and the TSV conductance measurement results have a relative error within 8.5%. We also perform an Monte Carlo simulation to prove that even under process variation, the proposed method can obtain a TSV capacitance within an absolute error of ±3 fF, obtain a TSV resistance with a relative error of no more than 18.4%, and obtain a TSV conductance of less than 100 ${\mu \Omega }^{{-1}}$ with a relative error of no more than 13%.

As an integrated circuit (IC) technology develops, 3-D stacked ICs based on through-silicon-via (TSV) technology have attracted the attention of the semiconductor industry. In 3-D stacked ICs, the TSV forms signal paths that vertically connect different ICs. The signal integrity largely depends on the quality of the TSV. A key challenge to the commercial viability of 3-D ICs is developing a method of accomplishing prebond TSV tests. To address this problem, we propose a prebond TSV test method with easily applied Design for Testability (DfT) structures and a simple fault-detection process. The proposed method is based on switched-capacitor circuits, which can detect TSV leakage faults, open faults, and high-resistance faults with high resolution. The fault-detection effectiveness is evaluated via HSPICE simulations. We also present an overall assessment of the test resolution, test time, and DfT area cost.